Prof. Steve Nowick was invited to join 2 leading national study committees sponsored by government agencies to define challenges and future research directions in two research frontier areas.
In March 2015, he attended the NSF Workshop on Ultra-Low Latency Wireless Networks in Phoenix, Arizona, a 2-day national study group, on the future of wireless technology to achieve extreme low-latency communication, both for macro-level networks and micro-level on-chip networks. He participated in drafting the final white paper report documenting outcomes of the workshop, that defines the challenges and opportunities of the area, and directions to achieve future breakthroughs. The report is expected to be used by NSF for defining its future funding initiatives.
In August 2014, he participated in the NSF/DARPA/DOE/NASA Workshop on System-on-Chip Design for High Performance Computing ("SoC for HPC") in Denver, Colorado, and gave an invited talk on his research on networks-on-chip (NoC's). This 2-day national study group, sponsored jointly by NSF, DARPA, DOE, NASA, and Sandia and Lawrence Berkeley National Laboratories, is on the future of designing cost-effective high-performance parallel computers for both Big Data and consumer applications. The workshop had under 35 attendees, with only 10 invited from academia, including Qualcomm's VP of Technology, Intel's director of future processor development, and NASA/JPL's manager of autonomous systems and flight computing. The outcome of this workshop is expected to shape the future landscape of high-performance computing.
