Speaker: Dr. Christos Vezyrtis, IBM T. J. Watson Research Center
Enterprise server chip design poses a hard power-supply noise problem. Increasing transistor counts and supply voltage scaling can create instantaneous changes in current, driving nanosecond-speed supply voltage (VDD) droops that require extra guard-band for correct product operation. The POWER9TM and z14TM processor use advanced mitigation techniques such as adaptive clocking and instruction throttling to ensure that processor functionality is maintained during power- supply droops. We will present the POWER9TM adaptive clocking strategy, embedding analog voltage-droop monitors (VDMs) that direct a digital phase-locked loop (DPLL) to immediately reduce clock frequency in response to a droop, and the z14TM advanced noise mitigation throttling options using the critical path monitor (CPM).
Christos Vezyrtzis received the B. Eng. degree from the National Technical University of Athens, Greece in 2006, and M.Phil, M.S. and Ph.D. degrees from Columbia University, New York, NY. He is now a Research Staff Member at IBM T.J. Watson Research Center, Yorktown, NY, and has served as Adjunct Assistant Professor at Columbia University, New York, NY. His research interests include high-speed mixed-signal and digital circuits. He was the recipient of the Best Paper Award for the Logic and Circuits track at IEEE International Conference on Computer Design (ICCD) in 2006. He has co-authored twelve patents.