Mooreâ€™s law drives lowering cost/function ratio and thus pushes addition of more functions on a chip. This requires reduction in power. In Internet of Everything (IoE), System on Chip (SOC), flexible electronics, 3D printing the drive towards low power while maintaining functionality will be essential. Also power has become the key driving force in high performance processor designs as the frequency scale-up is reaching saturation. In order to achieve low power system, circuit and technology co-design is essential. This talk focuses on pros and cons analysis of technology and circuit techniques from power perspective and various techniques to exploit lower power. The talk highlights fundamentals and the direction for low power optimization such as reduction in active, leakage, short circuit power and collision power will continue to be the focal area for in the scaled world. Conventional and advanced techniques (e.g. clock gating, power gating, longer channel, multi-Vt design, stacking, header-footer device techniques and new developments etc.) will be described for logic and memories. Finally key challenges in achieving low power will be described.
As the technology pushes towards sub-14nm era, process variability and geometric variation in devices can cause variation in power, performance and functionality. Predictive Analytics to capture systematic and random variation and to aid in robust design optimization in nm regime will be discussed. Also the talk will describe future growth directions and role of such predictive algorithms.
Dr. Rajiv V. Joshi is a research staff member at T. J. Watson research center, IBM. He received his B.Tech I.I.T (Bombay, India), M.S (M.I.T) and Dr. Eng. Sc. (Columbia University). His novel interconnects processes and structures for aluminum, tungsten and copper technologies which are widely used in IBM for various technologies from sub-0.5Âµm to 14nm. He has led successfully predictive failure analytic techniques for yield prediction and also the technology-driven SRAM at IBM Server Group. He commercialized these techniques. He received 3 Outstanding Technical Achievement (OTAs), 3 highest Corporate Patent Portfolio awards for licensing contributions, holds 58 invention plateaus and has over 225 US patents and over 350 including international patents. He has authored and co-authored over 185 papers. He received the Best Editor Award from IEEE TVLSI journal. He is recipient of 2015 BMM award. He is inducted into New Jersey Inventor Hall of Fame in Aug 2014 along with pioneer Nikola Tesla. He is a recipient of 2013 IEEE CAS Industrial Pioneer award and 2013 Mehboob Khan Award from Semiconductor Research Corporation. He is a member of IBM Academy of technology. He served as a Distinguished Lecturer for IEEE CAS and EDS society. He is IEEE, ISQED and World Technology Network fellow and distinguished alumnus of IIT Bombay. He is in the Board of Governors for IEEE CAS. He serves as an Associate Editor of TVLSI. He served on committees of ISLPED (Int. Symposium Low Power Electronic Design), IEEE VLSI design, IEEE CICC, IEEE Int. SOI conference, ISQED and Advanced Metallization Program committees. He served as a general chair for IEEE ISLPED. He is an industry liaison for universities as a part of the Semiconductor Research Corporation. Also he is in the industry liaison committee for IEEE CAS society.