Speaker : Dr. Rajiv Joshi , IBM
Mooreâ€™s law drives lowering cost/function ratio and thus pushes addition of more functions on a chip. This requires reduction in power. In Internet of Everything (IoE), System on Chip (SOC), flexible electronics, 3D printing the drive towards low power while maintaining functionality will be essential. Also power has become the key driving force in high performance processor designs as the frequency scale-up is reaching saturation. In order to achieve low power system, circuit and technology co-design is essential. This talk focuses on pros and cons analysis of technology and circuit techniques from power perspective and various techniques to exploit lower power. The talk highlights fundamentals and the direction for low power optimization such as reduction in active, leakage, short circuit power and collision power will continue to be the focal area for in the scaled world. Conventional and advanced techniques (e.g. clock gating, power gating, longer channel, multi-Vt design, stacking, header-footer device techniques and new developments etc.) will be described for logic and memories. Finally key challenges in achieving low power will be described.
As the technology pushes towards sub-14nm era, process variability and geometric variation in devices can cause variation in power, performance and functionality. Predictive Analytics to capture systematic and random variation and to aid in robust design optimization in nm regime will be discussed. Also the talk will describe future growth directions and role of such predictive algorithms.