Past Event

Energy-Efficient Digital Hardware and SoC Design: Design and Optimization Techniques

May 11, 2015
1:30 PM - 2:30 PM
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Speaker: Dr. Dongsuk Jeon, MIT

Speaker: Dr. Dongsuk Jeon, MIT

As CMOS technology has developed considerably in the last few decades, many SoCs have been implemented across different application areas due to reduced area and power consumption. Digital signal processing (DSP) algorithms are frequently employed in these systems to achieve more accurate operation or faster computation. However, CMOS technology scaling started to slow down recently and relatively large systems consume too much power to rely only on the scaling effect while system power budget such as battery capacity improves slowly. In addition, there exist increasing needs for miniaturized computing systems including sensor nodes that can accomplish similar operations with significantly smaller power budget.

Voltage scaling is one of the most promising power saving techniques due to quadratic switching power reduction effect, making it necessary feature for even high-end processors. However, in order to achieve maximum possible energy efficiency, systems should operate in near or sub-threshold regimes where leakage takes significant portion of power.

In this talk, a few key energy-aware design approaches will be described. Considering prominent leakage and larger PVT variability in low operating voltages, multi-level energy saving techniques to be described are applied to key building blocks in mobile applications: architecture study, algorithm-architecture co-optimization, and robust yet low-power memory design. Finally, described approaches are applied to design examples including a visual navigation accelerator, ultra-low power biomedical SoC and face recognition accelerator, resulting in >10x power savings than state-of-the-art.


Dongsuk Jeon received a B.S degree in electrical engineering from the Seoul National University, South Korea, in 2009 and a Ph.D. degree in electrical engineering at the University of Michigan, Ann Arbor in 2014. He is currently a postdoctoral associate at the Massachusetts Institute of Technology, where he is designing a versatile 3-D computer vision processor. His research interests include energy efficient signal processing, subthreshold circuit and SoC for mobile applications.