Date: Thursday, Aug. 21
Time: 1:00 PM - 2:00 PM
Location: CEPSR 707
Seminar: “Multibit Tilting PUFs (Physical Unclonable Functions) – where Process Variation is a Feature, not a Bug”
Speaker: Prof. Joseph Shor (CU EE PhD ’98, CU EE MS ’88), Bar Ilan University
Host: Mingoo Seok
Abstract: We each have biological identifiers, such as fingerprints, DNA, and retinal scans, which uniquely classify us. These can be useful to access secure areas such as our phones and computers. In a similar manner, it is essential for integrated circuits to generate secure and unique functions to identify specific chips during encryption and authentication protocols. In the past 15-20 years a category of circuit has emerged called “Physical Unclonable Functions (PUF)” which addresses this application. These circuits utilize the natural variation in fabrication process parameters to either generate a secret key or authenticate a transaction. Each chip is unique in this respect and the codes generated are hidden even from the manufacturers and IC designers. In general, process variation is a problem in integrated circuits, especially analog circuits. However, for this application, it is an essential asset.
A very good example of such a circuit is the simple latch, or SRAM cell. If there is a significant mismatch between the SRAM inverters, this cell can wake up in a logical state which is repeatably across multiple readings. The code thus generated by multiple SRAM bits can then be utilized to enable secure transactions. The challenge arises when the inverters are closely matched, and the logical state of the cell will vary between readings due to noise. Such a cell is “unstable” as a PUF and will generate errors in the subsequent code. There are error correction codes (ECC) which can be applied, but these are very costly in power, latency and area.
Recently, our group has developed a preselection algorithm we call “tilting”, whereby unstable PUF cells can be identified and can be excluded from the code. This yields a much more power-efficient PUF since complex ECC codes are not required. A method to extract multiple stable bits from a single cell using this technique has also been developed. During this talk the application and circuitry of PUFs will be explained, and the development of stable PUFs using tilting will be detailed. Finally, we will show the industrial adaptation of this method at several semiconductor companies.
Bio: PhD and MS in Electrical Engineering from Columbia University, 1993 and 1988 respectively. BA in Physics, Queens College, 1986. Prof. Shor has published more than 70 papers in refereed Journals and Conference Proceedings in the areas of Analog Circuit Design and Device Physics. He holds over 50 issued patents and several pending patents. He is presently a Full Professor of Electrical Engineering at Bar Ilan University. From 2004-2015, he was at Intel, as a Principal Engineer, and head of the Analog Team at Intel Yakum. Between 1999-2004, he worked at Saifun Semiconductor as a Staff Engineer where he established analog activities for Flash and EEPROM NROM memories. From 1994-1999, he was a Senior Analog Designer at Motorola Semiconductor, in the DSP Division. From 1988-1994, he was a Senior Research Scientist at Kulite Semiconductor, where he developed processes and devices for Silicon Carbide and Diamond Microsensors. His present interests include Low Power Analog circuits, Switching and Linear Voltage Regulators, Sensors, PLLs and IO circuits, Microprocessors and Security.He was a member of the ISSCC Technical Program Committee (TPC) from 2014-2018 and is presently a member of the TPC and Steering Committee of the European Solid State Electronics Conference (ESSCERC).He was an Associate Editor for IEEE SSCL and IEEE Sensors. He has been a guest Associate Editor of JSSC and SSCL.