Events

Past Event

EE Seminar: Design Flow Tuning for Optimizing Industrial Server Processors and AI Accelerators

April 29, 2022
11:00 AM - 12:00 PM

Speaker: Matthew Ziegler
Location: MUDD 627, Columbia University
Zoom link: https://columbiauniversity.zoom.us/j/2096068112
Host: Prof. Mingoo Seok 

Abstract

The complexity of modern logic and physical synthesis tools leads to a vast design space that is difficult even for experienced human designers to navigate. Fortunately, machine learning approaches and cloud computing environments are well suited for tackling complex parameter tuning problems like those seen in VLSI design flows. This talk discusses design flow tuning approaches utilized for optimizing IBM server chips over the last several processor generations. A holistic approach is proposed that blends online and offline machine learning techniques for industrial design flow tuning. This talk also focuses on recent work at IBM for AI acceleration using custom hardware. The broader effort spanning the hardware/software stack is reviewed. Specific focus is given to AI chip design, ASIC design flow tuning, and potential new directions for design flow tuning research.

Bio

Matthew Ziegler is a Principal Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY. He received the Ph.D. degree in electrical engineering from the University of Virginia, Charlottesville, in 2004. Since joining IBM Research in 2004, he received several technical accomplishment awards in the areas of processor design, design automation, and low power design. He is currently the physical design and methodology lead for IBM’s AI acceleration ASIC effort. Dr. Ziegler’s research has recently focused on AI accelerator design, machine learning for CAD, and VLSI design productivity. He is a recipient of the 2018 Mehboob Khan Award from the Semiconductor Research Corporation and is a member of the IBM Academy of Technology. He has served on various conference committees, including General Chair for ISLPED 2019, Program Chair for the 2018-2021 IEEE IBM AI Compute Symposia, and Track Co-Chair for DAC 2022. He has authored over 100 combined peer reviewed papers and issued patents.