Speaker: Prof. Tae-Hyoung Kim, Nanyang Technological University
Recently, various ultra-low power applications such as wearable devices, biomedical devices and Internet-of-Things (IoT) have been developed opening up a new domain of integrated circuits design. In these applications, ultra-low power circuit techniques for improving the energy efficiency have been the main research focus. One of the most challenging blocks in ultra-low power systems is SRAM. A number of state-of-the-art circuit techniques have been proposed to tackle the ultra-low power SRAM design issues. In this talk, I will briefly explain various design issues in SRAM followed by various state-of-the-art design techniques. Some recent research works from my research group in NTU will also be introduced.
Prof. Tae-Hyoung Kim received the B.S. and M.S. degrees in electrical engineering from Korea University, Seoul, Korea, in 1999 and 2001, respectively. He received the Ph.D. degree in electrical and computer engineering from University of Minnesota, Minneapolis, MN, USA in 2009. From 2001 to 2005, he worked for Samsung Electronics where he performed research on the design of high-speed SRAM memories, clock generators, and IO interface circuits. In 2007 ~ 2009 summer, he was with IBM T. J. Watson Research Center and Broadcom Corporation where he performed research on circuit reliability, low power SRAM, and battery backed memory design, respectively. On November 2009, he joined Nanyang Technological University as an assistant professor.
He received 2016 International Low Power Design Contest Award from ISLPED, a best paper award at 2014 and 2011 ISOCC, 2008 AMD/CICC Student Scholarship Award, 2008 Departmental Research Fellowship from Univ. of Minnesota, 2008 DAC/ISSCC Student Design Contest Award, 2008, 2001, and 1999 Samsung Humantec Thesis Award and, 2005 ETRI Journal Paper of the Year Award. He is an author/co-author of +100 journal and conference papers and has 17 US and Korean patents registered. His current research interests include low power and high performance digital, mixed-mode, and memory circuit design, ultra-low voltage circuits and systems design, variation and aging tolerant circuits and systems, and circuit techniques for 3D ICs. He serves as an associate editor of IEEE Transactions on VLSI Systems. He is an IEEE senior member and the Chair of IEEE Solid-State Circuits Society Singapore Chapter. He has served numerous conferences as a committee member.