Custom Circuits
In this project, besides the NPU core, we have designed three types of circuits at the transistor level: an input buffer for driving the NPU core, an output buffer for driving external circuits, and a Schmitt trigger for processing clock signals.
Input buffer
The input buffer features a two-stage design. This design specifies a PMOS/NMOS width ratio of 2.6/1, aimed at closely matching their rising and falling times. In the first stage, the buffer employs 2.5V devices. These devices have a thicker oxide layer compared to 1V transistors, offering enhanced Electrostatic Discharge (ESD) protection. The second stage incorporates 1V devices, indicative of lower capacitance, which is beneficial for faster switching speeds and reduced power consumption. The buffer is designed to drive a 1pf load. The simulation results gives a rising time of 1.56ns and a falling time of 1.30 ns.
Figure 1. Input buffer schematic
Figure 2. Input buffer simulation results
Figure 3. Input buffer layout
Output buffer
Like the input buffer, it maintains the same PMOS/NMOS width ratio of 2.6/1. 1V devices are used in the first three stages of output buffer, and the subsequent stages use 2.5V devices. The scaling of each stage being three times larger than the previous one, ensuring that the final stages are robust enough to handle the 10pf load efficiently. The simulation results shows a rising time of 1.30ns and falling time of 1.52ns.
Figure 4. Output buffer schematic
Figure 5. Output buffer simulation results
Figure 6. Output buffer layout
Schmitt tigger
The Schmitt trigger is designed to enhance the quality and stability of clock signals. It possesses distinct rising and falling thresholds, a characteristic known as hysteresis. This hysteresis is instrumental in eliminating unnecessary switching caused by signal noise or instability. It ensures that the edges of the clock signal are clear and well-defined, making the rising and falling edges of the clock signal steeper and more distinct. This feature is crucial in digital circuits, as it contributes to the overall reliability and precision of signal processing. The Schmitt trigger in this project is designed using 2.5V thick-oxide devices. It has hysteresis of 56mV and midpoint voltage of 527.5mV.
Figure 7. Schmitt trigger schematic
Figure 8. Schmitt trigger simulation results
Figure 9. Schmitt trigger layout