This project presents the ASIC implementation and tape out of a RISC-V processor in TSMC 65nm technology. The project was part of the "EE6350 - VLSI Design Lab" class offered at Columbia University by Prof. Peter Kinget and was co-supervised by Prof. Mingoo Seok and sponsored by Apple Inc.

In this work, we present the integration of the open source Ibex 32-bit RISC-V CPU core [1] with SPI, UART and GPIO communication peripherals and on-chip memory to produce a complete System-on-Chip (SoC) that supports multiple functionalities and can interact with a user in real time. To achieve that, we followed the typical design cycle including both frontend and backend flows, such as RTL design and verification, logic synthesis, automatic placement and routing and pad integration.

The design phase took place during the Spring 2024 semester and the chip was fabricated by TSMC in the 65nm technology node over the summer. The die photo of the chip is shown in Figure 1. The PCB design and chip bring-up and testing happened during the Fall 2024 semester.