Overall, we succesfully designed, implemented and taped-out a fully functional System-on-Chip based on the Ibex 32-bit RISC-V CPU core. We integrated open-source communication peripherals with an AHB Bus, defined the underlying memory mapping and generated on-chip SRAM memory for instructions and data with the ARM Artisan Compiler.

To achieve correct functionality, we studied in depth how a processor works including what operations are executed in each cycle and how the processor state is affected. We integrated the RTL with the RISC-V GNU toolchain to perform RTL Verification. We went through the entire backend design flow and performed Placement & Routing, Static Timing Analysis, Power Analysis to ultimately generate the GDSII file.

After chip fabrication, we designed a PCB that would facilitate the chip's functionality demonstration by simplifying the peripheral device integration and would allow portability by integrating battery cells for power supply. Lastly, we wrote and compiled a multi-function C program that stressed all the communication peripherals and proved that our System-on-Chip is fully functional.