1. Verilog to Routing. Web.
  2. Y. Kim, Y. Lee, D. Sylvester, and D. Blaauw, "SLC: Split-control level converter for dense and stable wide-range voltage conversion," in Proc. ESSCIRC, Sep. 17-21, 2012, pp. 478-481.
  3. W.-T. Wang, M.-D. Ker, M.-C. Chiang, and C.-H. Chen, "Level shifters for high-speed 1-V to 3.3-V interfaces in a 0.13-um Cu-interconnection/low-k CMOS technology," in Proc. IEEE Int. Symp. VLSI Technology, Systems, Applications, 2001, pp. 307-310.
  4. M.-D. Ker, T.-M. Wang, and F.-L. Hu, "Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process," in Proc. IEEE Int. Conf. Electron., Circuits, Syst., 2008, pp. 1047-1050.
  5. Shyamapada Mukherjee and Suchismita Roy. Article: Testing the Effect of different Switch Box Architectures on Detailed Routing in FPGA. IJCA Proceedings on International Conference on Communication, Circuits and Systems 2012 iC3S(5):1-5, June 2013.
  6. Chiasson, Charles, and Vaughn Betz. "Should FPGAS Abandon the Pass-Gate?" 2013 23rd International Conference on Field Programmable Logic and Applications (2013).
  7. Schmit, Herman, and Vikas Chandra. "FPGA Switch Block Layout and Evaluation." Proceedings of the 2002 ACM/SIGDA Tenth International Symposium on Field-programmable Gate Arrays - FPGA '02 (2002).
  8. Weste, Neil H. E., David Money. Harris, and Neil H. E. Weste. CMOS VLSI Design: A Circuits and Systems Perspective. Boston: Pearson/Addison-Wesley, 2005. Print.
  9. Betz, Vaughn, Jonathan Rose, and Alexander Marquardt. Architecture and CAD for Deep-submicron FPGAs. Boston: Kluwer Academic, 1999. Print.

Back to top