Trollstigen has 8X8 array of tiles with 16 GPIOs+8 HIP ports. The chip also integrated level conversion circuitry (1.2V core<->3.3V I/O) into IO blocks.Verilog is synthesized to bitstream from software flow developed by us through FPGA's asynchronus 8-bit parallel bus. Configuration data is stored in distributed 8X8 cell blocks.
FPGA block level architecture
Level Converters & Output Driver
The level converter has the feature of no contention and fast voltage level convertion with 24mA drive strength with low output impedance . Furthermore, a bus keeper is added into the design.