The Trollstigen FPGA is one of the first physical realizations of a homogeneous FPGA design conceived using the open-source Verilog-to-Routing (VTR) FPGA CAD flow. The FPGA and its underlying sub-designs -- including the core logic, memory, reconfigurable routing, bidirectional level-shifting I/O, clock distribution, and power distribution -- all function correctly as judged from the successful implementation of several demos, some of which approach full fabric utilization.

The designers would like to thank Professor Kinget for the valuable opportunity to experience the entire IC design flow, and Professor Seok for his design advice throughout the project. The designers also thank Ph.D. students Vivek Mangal, Doyun Kim, and Josh Seongjong Kim for their assistance with mixed-signal and digital EDA tools at several points during the semester.