In this section, the layout of the whole chip and each building block in the chip are shown.

Floorplan

Figure 1 and 2 show the floorplan and whole layout for the chip.

Figure 1: Chip Floorplan

Figure 2: Chip Layout

Triangle wave generator

Figure 3: Miller OTA Layout

Figure 4: Single-ended to Differential Converter Layout

OTA

Figure 5: Triangle Wave Generator Layout

Comparator

Figure 6: NMOS Input Comparator Layout

Figure 7: PMOS Input Comparator Layout

Non-overlapping clock generator

Figure 8: Non-overlap Clock Generator layout

Current mirror

Figure 9: Cascode Current Mirror Layout

Output driver

Figure 10: Output Driver Floorplan

Figure 11: Output Driver Layout

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