Layout

Figure 1. Overall layout

The overall layout of the chip is shown above. The floorplan of the whole signal chain is symmetric, with the output driver taking the most space to provide large driving strength. All the empty spaces left are filled with Decoupling caps to reduce ringing on the rails.

OTA

Figure 1. OTA layout


Single-ended to differential converter

Figure 2. single-ended to differential converter layout


Comparator

Figure 3. comparator layout


Triangle wave generator

Figure 4. Triangle wave generator layout


Nonoverlapping generator

Figure 5. Non-overlapping generator layout


Current Mirror

To reduce mismatches, the current mirrors are laid out as close as possible. Additionally, the MOSFETs receiving the Iref are always in the center, while other MOSFETs are laid out symmetrically.


Figure 7a. Current mirror(1:1) layout

Figure 7b. Current mirror(1:15) layout


Output driver & pre-drivers

Figure 8. Output driver and pre-drivers layout


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