References

  1. Jiann-Jong Chen et al., "Sub-1V capacitor-free low-power-consumption LDO with digital controlled loop," in Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on , pp.526-529, Nov. 30 2008-Dec. 3 2008
  2. Gabriel Rincon-Mora, Analog IC Design with Low-Dropout Regulators, Second Edition, McGraw-Hill Education, 2014
  3. Jia-Hui Wang et al.., "A low voltage and low ground current low-dropout regulator with transient enhanced circuit for SoC," in Green Circuits and Systems (ICGCS), 2010 International Conference on , pp.428-431, 21-23 June 2010
  4. Jianping Guo et al.., "A 6- uW Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology," in Solid-State Circuits, IEEE Journal of , vol.45, no.9, pp.1896-1905, Sept. 2010
  5. Wei-Chung Chen et al.., "17.10 0.65V-input-voltage 0.6V-output-voltage 30ppm/°C low-dropout regulator with embedded voltage reference for low-power biomedical systems," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International , vol., no., pp.304-305, 9-13 Feb. 2014
  6. Sau Siong Chong et al.., "A Sub-1 V Transient-Enhanced Output-Capacitorless LDO Regulator With Push–Pull Composite Power Transistor," in Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.22, no.11, pp.2297-2306, Nov. 2014
  7. Yu-Huei Lee et al.., "A 65nm sub-1V multi-stage low-dropout (LDO) regulator design for SoC systems," in Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on , pp.584-587, 1-4 Aug. 2010
  8. Pui Ying Or et al.., "An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection," in Solid-State Circuits, IEEE Journal of , vol.45, no.2, pp.458-466, Feb. 2010
  9. Xiao Liang Tan; et al. ., "A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF–10 nF Capacitive Load," in Solid-State Circuits, IEEE Journal of , vol.49, no.11, pp.2658-2672, Nov. 2014


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