Intro

Welcome to the home page of EE6350 VLSI Design Lab for Spring 2015.

This graduate course focuses on the design, simulation, layout, verification and tape-out of an IC design. MOSIS is offering access to an IBM 0.18um CMOS technology for this course. MOSIS fabricates the chips that students subsequently test.

Please see below for the Student Feedback and the Project Reports and Videos

Spring 2015 Project Reports and Videos


Analog filter synthesized with a digital flow

Scott Newton

Publication: S. Newton and P. R. Kinget, "A 4th-Order Analog Continuous-Time Filter Designed Using Standard Cells and Automatic Digital Logic Design Tools," IEEE International Symposium on Circuits and Systems (ISCAS), May 2016.

PROJECT DESCRIPTION & REPORT


VCO-based low-dropout voltage regulator

Sanket Gupta and Zhongjie Dai

Publication: Z. Dai, S. Gupta, S. Kalani and P. R. Kinget, "3.7uW 0.8V VCO-Integrator-Based High-Efficiency Capacitor-Free Low-Dropout Voltage Regulator," IEEE International Symposium on Circuits and Systems (ISCAS), May 2016.

PROJECT DESCRIPTION & REPORT


Class-D amplifier with off-the-shelf FM radio

Alexandar Gazman and Hang Guan

PROJECT DESCRIPTION & REPORT


PPG heart-rate monitor

Qirui Xu and Jian Shao

PROJECT DESCRIPTION & REPORT


Digital clock

Yandong Li and Yuanpei Zhang

PROJECT DESCRIPTION & REPORT


Integrated Oscillators

Aida Berrios

PROJECT DESCRIPTION & REPORT


Class-D amplifier

Jihua Li and Yufei Wang

PROJECT DESCRIPTION & REPORT


PPG heart-rate and respitory-rate monitor

Girish Ramakrishnan and Olivier Jin

PROJECT DESCRIPTION & REPORT