Conclusions
All the blocks and features are functional as expected in correct configuration. The clock is very accurate. The whole system is around 1 second slower every 10 hours, when compared to a smartphone stopwatch. The chip's accuracy is almost as good as the crystal.
References
[1] N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th edition. Boston: Addison-Wesley, 2010.
[2] S. Brown and Z. Vranesic, Fundamentals of Digital Logic with Verilog Design, 3rd edition. New York: McGraw-Hill, 2014.
[3] J. F. da Rocha, M. B. dos Santos, J. M. Dores Costa and F. A. Lima, "Level Shifters and DCVSL for a Low-Voltage CMOS 4.2-V Buck Converter," in IEEE Transactions on Industrial Electronics, vol. 55, no. 9, pp. 3315-3323, Sept. 2008, doi: 10.1109/TIE.2008.927974.
[4] I. M. Filanovsky and H. Baltes, "CMOS Schmitt trigger design," in IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 41, no. 1, pp. 46-49, Jan. 1994, doi: 10.1109/81.260219.
[5] Power-on-Reset: https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3227.html
Acknowledgments
We are all very thankful to Prof. Peter Kinget for this precious opportunity to study and design our own chip, as well as providing valuable guidance in silicon design and testing. We also received a lot help from course TA Rui Xu, who spent a lot time with us to improve our chip design and guided us through the whole process. We are also thankful for the generous sponsorship from Apple Inc to make all these possible. Finally, we would like to express our gratitude to the whole TA team and all the ones tho helped us in the whole project.