IC Layout

top-level-layout

Fig 1. Top-Level receiver layout (cadence).


The overall Chip Layout is shown above.

RF FRONT-END (RFFE) LAYOUT:

  • LNA LAYOUT:

    • lna layout

    Fig 2. LNA layout and schematic (cadence).


  • LO DRIVER LAYOUT:

  • MIXER LAYOUT:

    • lna layout

    Fig 4. Mixer layout and schematic (cadence).


    IF AMPLIFIER (IFA) LAYOUT:

    ifa single-stage layout

    Fig 5. IFA single-stage layout and schematic (cadence).


    VCO Block:

    VCO Layout

    Detector Block :

    Detector Layout

    Biasing Block :

    Biasing RF Layout

    Biasing IF Layout

    Biasing Det Layout



    Back to top