IC Layout
Fig 1. shows the top-level layout of our chip. It contains digital core which is automatically generated by Cadence Innovus. Other layout of analog components, such as display driver, level shifter, buzzer/LED driver, are all created manually using Cadence.
Fig 2. presents the detailed version of digital core layout. The size of digital core layout is 218 x 218. And the corresponding density is abuout 35%. As mentioned above, it is created by following standard ASIC flow.
