IC Design
The overall circuit design process can be seperated into Digital Design and Analog Design.
Digital Design
Defining Requirements and High-Level Architecture:
Define Requirements: Understand and document the functional and performance requirements of the ASIC. This involves detailed discussions with stakeholders to gather information about the intended application and desired features.
High-Level Architecture: Develop a high-level architectural design that outlines the major functional blocks and their interconnections. This serves as a blueprint for the subsequent design phases.
RTL Design and Functional Verification:
RTL Design (Register Transfer Level): Create a detailed digital logic design using a hardware description language (HDL) such as Verilog or VHDL. This involves specifying how data is transferred between registers.
Functional Verification: Simulate the RTL code to ensure that the design behaves as expected. This step helps catch design errors and ensures that the RTL code meets the specified requirements.
Synthesis and Technology Mapping:
Logic Synthesis: Convert the RTL code into a gate-level netlist, a representation of the design using logic gates.
Technology Mapping: Map the synthesized logic to the target technology library, which contains information about the available logic gates and their characteristics.
Physical Design:
Floorplanning: Plan the physical layout of the ASIC by allocating space for different functional blocks and defining their approximate locations on the chip.
Placement: Place the synthesized gates on the chip according to the floorplan, considering factors like signal integrity and power distribution.
Clock Tree Synthesis (CTS): Design the clock distribution network to ensure synchronous operation across the entire chip.
Routing: Create metal interconnections between different components, ensuring efficient communication between functional blocks.
Timing Closure and Optimization:
Static Timing Analysis (STA): Analyze and optimize the timing of the design to meet performance requirements. This involves ensuring that signals reach their destinations within specified time constraints.
Optimization: Iteratively refine the design to achieve timing closure and optimize for factors such as power consumption and area utilization.
Physical Verification:
Design Rule Checking (DRC): Ensure the design complies with the foundry's manufacturing rules by checking for violations of physical design constraints.
Layout vs. Schematic (LVS): Verify that the layout matches the expected circuit as described in the schematic.
Simulation and Power Analysis:
Post-layout Simulation: Simulate the design using the final layout to verify functionality and identify any issues introduced during the physical design phase.
Power Analysis: Analyze power consumption and optimize the design to meet power targets, considering factors such as dynamic and static power.
GDSII Generation:
Generate GDSII Files: Create the final set of files in Graphic Data System II (GDSII) format. These files contain the geometric information necessary for semiconductor manufacturing.
Testing:
Final Testing: Test the manufactured ASIC to ensure it meets specifications. This includes functional testing, performance testing, and often involves using automated test equipment.
Analog Design
Level Shifter
For the level shifter, we selected a cross-coupled level shifter, used 1v-based devices as input and first half part, and used 2.5v devices as output and second half part. We repeatedly adjust their sizes to achieve the ideal output waveform and value.
Buzzer/LED Driver
For the driver, the steps for the buzzer and single-led driver are the same, the NMOS should work under linear region which is a switch when it been turned on. The "switch" should have low ON resistance but needs to drive a large enough current for the hardware. We first varied the width of the MOSFET and found the ideal total width that meets the current drive requirement, and next we varied the width to find the on-resistance to further find the ideal MOSFET which width, finger, and multiple can meet both current drive and low resistance requirement as the analog driver.
Display Driver
The 7-segment driver needs to do this step both for NMOS and PMOS, the driver consists of two parts because of the special structure of the 7-segment led. We also compared the common-cathode and common-anode connection, the area of the common-cathode's driver is smaller, so we decided to use the common-cathode.