System Overview
Top Level Block Diagram
Fig: Top Level Chip Architecture
Our amplifier operates in Class-D mode, where final switches serve as a power(current)-boosting stage. The signal follows a left-to-right path: an audio signal transforms into two differential signals via a single-ended to differential converter. Each is integrated and compared with a triangular wave, producing PWM signals.
These PWM signals enter non-overlap generators, delaying rising or falling edges, ensuring there is no overlap between the PMOS and NMOS in the Final Driver. This generates a deadtime that in turn prevents shoot through losses and also prevents the final drivers from burning off due to high transient shoot-throughs.
Integrator’s RC decide the overlap loop’s first pole location
Non-overlap generators are pivotal. They prevent simultaneous activation of low-side and high-side switches by delaying clock pulses, preventing a VDD-to-ground short. This meticulous design safeguards efficiency and curtails power wastage.
Gain control resistors are off chip potentiometers to adjust the volume
Tone control block, boosts/suppresses certain range of frequencies
Further details on individual block specifications and designs follow.
Top level Model for stability analysis
(Half circuit analysis)
Fig: Half Circuit model for stability analysis
We model a basic single-ended audio amplifier system. This straightforward representation extends seamlessly to the fully differential structure, with Vout connected differentially.
Within this model, we introduce an idealized loop featuring an integrator with a Unity-Gain Bandwidth (UGB) denoted as ωUGB,int. The PWM and output driver form a unified block, introducing a delay (τ) and a gain (GPWM). This simplification allows us to define the loop gain, a crucial parameter influencing the amplifier system's behavior.
Fig: Ramp generator gain calculation
Above figure shows the gain that we get from the ramp generator:
GPWM =Vop/Vtp= Vdd/Vramp_pp
The loop gain is then given by:
Where:
Finally Loop gain becomes:
From the above analysis we can calculate the amount of delay we can tolerate for a decent phase margin of 60 degrees
We also, however, need OTA with significantly high UGB (>>20kHz) for this approximation to be valid, and significantly high DC gain in the OTA (>60dB)
Sources of Tdelay (Every small source of delay needs to be accounted for):
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Comparator Delay
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Comparator Hysteresis translating into delay (due slow ramp of 2us)
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Non Overlap generator delay
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Pre driver delay
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Output driver delay
Fig: Integrator loop response
From here we get that the Integrator UGB (1/RC) is set to 55kHz to be able to support the entire audio bandwidth (~20kHz). This UGB if integrator decides the first pole location of the entire top level loop, which needs to be sufficiently low, to have good phase margin, hence the pole is chosen to be 55kHz.