Other Block Level Designs
Triangular Wave generator
This circuit, based on a relaxation oscillator (Fig. 3), produces a triangular waveform for translating input signals into pulse width modulation. The oscillation period depends on the capacitor's charging and discharging slew rate (I/C). VMAX and VMIN are externally generated using a resistive divider network.
Fig: Triangle wave generator Schematic
Fig: Triangle wave generator Symbol
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Not much variation in frequency because of the external cap. Internal Cap would add +- 20% variation.
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Controllability: Ramp Bias current, Vref high & Vref low. Can tune frequency as well as peak to peak with these options
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Visibility: Test pin for ramp output
Fig: Triangle wave generator TB
Fig: Simulation Results
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Linearity: Derivative of ramp shows it is fairly linear
Fig: Triangle wave gen layout
All matched elements are common centroid matched
The Three Comparators
A. Signal Path Comparator
Fig: Signal Path comparator Schematic
Fig: Comparator Symbol
The signal path comparator is used to convert the integrator output into PWM signals as they are compared with triangular waveforms from the ramp generator. The topology used was nmos differential input pair with cross coupled pmos loads along with diode connected pMOS loads as core. For this to function as a comparator the size of cross coupled pairs should be larger than the diode connected loads and their ratio was 2:1 respectively. The hysteresis achieved is ~50mV. The second stage converts differential outputs into single ended output. The rise time and fall time of this comparator are important as this plays a role in determining the dead time needed in our system and hence the THD too!
Fig: Comparator Layout
Fig shows the layout for the signal path comparator. All nMOS current mirrors and pMOS loads are common centroid matched. The input devices are in the middle and the second stage is on the right side. All signals are routed differentially.
B. Comparators for Ramp Generator
Two different comparators are designed for the ramp generator. One with nMOS input pair for higher Vref level and other with pMOS input pair for lower Vref level.
Similar topology was used for these comparators. However, These comparators are lower power, slower and with higher hysteresis than top level comparators. However the load widths have a ratio of 4:1 for hysteresis of ~207mV.
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NMOS Comparator
Fig: Comparator Layout
Fig: Comparator Schematic
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PMOS Comparator
Fig: Comparator Schematic
Fig: Comparator Layout
Non Overlap Generator
Non-overlap clock generators produce clock pulses with edges that never overlap simultaneously, ensuring a distinct delay between them. The design is straightforward, with the critical consideration being the optimal delay. Fig. depicts the schematic, utilizing a capacitor-inverter chain in the latch feedback for varied triggering times. The layout in Fig. 9 is sizable due to the use of MOM capacitors, occupying a significant area.
These PWM signals enter non-overlap generators, delaying rising or falling edges, ensuring there is no overlap between the PMOS and NMOS in the Final Driver. This generates a deadtime that in turn prevents shoot through losses and also prevents the final drivers from burning off due to high transient shoot-throughs.
Non-overlap generators are pivotal. They prevent simultaneous activation of low-side and high-side switches by delaying clock pulses, preventing a VDD-to-ground short. This meticulous design safeguards efficiency and curtails power wastage.
Fig: Non Overlap Gen Schematic
Fig: Non Overlap Gen Symbol
Fig: Non Overlap Gen Layout
Decaps take most of the area of the Non Overlap generator.
Fig: Non Overlap Gen TB
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Controllability: External Board cap. Can be changed to control delay and hence deadtime.
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Visibility: Can monitor the gates of the final FET to measure deadtime
A total off chip cap of 2p (trace cap + no external cap) the delay is around 580ps
To get a delay of 10ns we need around 139pf cap bank on board.
Deadtime is chosen based on the final driver’s gate’s rise/fall times.
Finally during chip-bringup, the deadtime was chosen to be 2ns (Based on shoot-through vs THD tradeoff)
Bias Generator
Fig: Bias Gen Schematic
Cascode bias generation based on the following structure(low voltage cascode voltage generator):
Fig: Single current mirror cell layout
Common centroid matched
Fig: Bias Gen TB
The typical values of Res needed to generate 5uA, 10uA and 20A, are 34K, 78K and 200K respectively
Miller OTA
Used in Tone Control and Adder
Fig: Miller OTA Schematic
Fig: Miller OTA TB
Fig: Miller OTA Layout
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Input Devices - Common Centroid matched.
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Current Mirrors - Common centroid matched, blocks layout.
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Capacitor planned to arrange across transistors (as shown).
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Dummies used as Decaps too - MOSCAP
Active Baxandall Tone Control
The Active Banxandall Tone Control is an electronic circuit used in audio systems to adjust the frequency response, specifically the bass and treble levels. It's an active tone control design that allows for both boosting and attenuating bass and treble frequencies independently. The circuit typically includes amplifiers and adjustable filters for each frequency range, providing a more versatile and customizable audio adjustment compared to passive tone control circuits.
All Rs, Cs and Potentiometers Off Chip
Fig: Tone Control Block Schematic
Fig: Tone Control Simulation results
Decoupling Capacitor Cell
MOS-Cap + MOM caps are used as a decoupling capacitor. The fig shows the layout for the same. All odd metal layers are stacked for source-drain connection and all even metal layers for gate connection. This was done to get additional parasitic capacitance from stacked metals.
Fig: Unit Decoupling Cap cell layout
Fig: Unit Decoupling Cap cell schematic