Challenges and Solutions
In this section we will discuss the major roadblocks that we faced during the design and chip bring-up cycle, and how we fixed them. These highlight our major learnings from this course.
Efficiency degradation due to bond wire parasitics (Pre Silicon)
Problem: High Resistance of Bond Wire were leading to increased conduction losses which severely affected our efficiency (25-30% degradation in efficiency just because bond wire resistances). The switches were designed to have 80 mOhm of resistance, and then Bond Wires started adding 610 mOhms of resistance in series severely hurting our efficiency
Fig: Bondwire model, shows 610 mOhms of BW resistance
Solution: Dedicate 30/64 pins to VDD, GND and Outputs. We got back ~25% lost efficiency.
Fig: Final Pinout of the chip
Half of the available pins dedicated to the output path to improve Efficiency
Common Mode problem in the Fully Differential Amplifier (Pre Silicon)
Problem: Initial architecture of the FDA had two stable operating points→ Probability of the getting stuck at 0 Vcm during startup
Solution: We analyzed the structure and figured out that if the CMFB is fed to the NMOS tail current source, then the circuit has two stable operating points. This is because when everything ramps up, the NMOS tail current source is at linear region and CMFB tries to pull the gate node up, which pushes the NMOS tail current source further into the linear region, while the PMOS current loads get stuck at cutoff. The circuit has no way to recover from this. And hence the circuit can be stuck at 0 Vcm at startup. Instead, however, if the CMFB is fed to the PMOS current loads, the CMFB now pull the PMOS loads away from cutoff and hence the circuit always recovers.
Fig: DC Operating point Sims of the older and fixed topologies
Ref: A. Tauro, C. Marzocca, C. T. Francesco, and A. Di Giandomenico, “Common mode stability in fully differential voltage feedback CMOS amplifiers,” in 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, Dec. 2003, vol. 1, pp. 288-291 Vol.1. doi: 10.1109/ICECS.2003.1302033.
Supply switching-noise problem (Post Silicon)
Problem: We were seeing huge supply noise problems which were also glitching the ramp. This was because the ramp references were getting generated externally and device ground was different from the external ground
Solution: We added a lot of additional supply-decaps & ramp-reference-decaps on the surfboard to suppress the supply noise. And feed cleaner Ramp references. Onboard LDOs for the individual chip supply domains further improved the performance
Fig: Improvement in ramp signal by suppressing switching noise