Switch and Predriver Design
Predriver and Output Driver
Fig: Pre- Driver Schematic
Fig: Driver Schematic
Fig: Driver and Pre-driver Symbol
The pre drivers and drivers were designed together in a parameterized manner. In this technology for equal driving strength of pMOS and nMOS the sizing ratio is 2.7:1 respectively. The ratio of the next inverter is maintained at 10 times the present stage in the driver chains, as such scaling is a good compromise between Delay of chain, number of stages required in pre-driver and Efficiency. Each predriver chain finally drives one gate and hence the final ratio is 1:40 as opposed to 1:10. The pMOS gate driver chain has to drive 3x more capacitor than nMOS gate driver chain and hence is sized accordingly. One can see the sizing ratios maintained in Figure above.
Final switch size selected based on Efficiency vs W graph.
Fig: Model Efficiency vs unit cell width
Hence selected unit W was 3.5um making the final driver sizes 37.8mm/280nm and 14mm/280nm for pMOS and nMOS respectively for efficiency of ~94%. These devices are huge and hence add small on resistance of ~77mOhm each in the output path.
Fig below shows the layout details for the drivers. We made sure we have good substrate ties throughout our devices to avoid latch up issues. Wide traces of M9 and M8 to avoid electromigration and provide low trace resistance. Multiple metal layers were layered to make connections for reducing trace parasitics and current division.
Fig: Pre-driver and Driver Layout