Top Level IC Design
Top Level Pin Out
Fig: Pinout of chip
The power domain is divided into two parts: Analog side and Switching side, to reduce injection of switching noise (due to PWM signals) on the output side to the analog side.
On the switching side seven pins are dedicated to each output, and eight pins are given to Vdd_switching and VSS, to reduce bond wire resistance in the output path. There are two pins for Vdd_analog and VSS on the analog side.
Chip Top Schematic
Fig: Top Level Schematic
Top Level Key Signals
Fig: Simulated Signals
The topmost is the sinusoidal input signal coming to the chip. After that are the two differential outputs for amplifier and then integrator. These integrator outputs and Ramp are fed to comparators and hence we get out the two PWMs P and M. After filtering the differential PWM signals one gets the shown final output signal.
The zoomed image on right shows how the PWM signals duty cycle varies as per the input signals.
Top Level Floor Plan
Fig: Chip Layout
Fig: Chip Layout and Floor Plan
The total chip area is 1mm x 1mm, however only 0.89mm x 0.89mm area is actually available for the circuitry. The remaining area is occupied by the ESD cells.
The floor plan in figure above gives a clearer image of how different blocks are present inside of the chip. The green arrows on the floor plan shows our main signal path from audio input to final PWM output. Since, we have designed a fully differential class - d amplifier, the left and right channel signal paths are placed symmetrically about the x-axis.
The top level routing is done with wide traces in topmost metals in the stack i.e. M8 and M9. These metals have the capacity of delivering power more efficiently. After completion of the top level layout and routing, the empty spaces are filled with decoupling capacitor cells. Most of the decoupling areas were dedicated to Vdd-switching and few decoupling areas to Vdd-analog, since drivers inject a lot of switching noise in Vdd-switching and Gnd.
Top Level Pad and Package Parasitics
Fig: Hierarchical view of chip
The small die can be seen in the leftmost picture of the actual package. The package is huge compared to this actual die and hence adds a lot of parasitics. These package and bond wire parasitics were included in simulations as shown in the second and the third picture.