Block Description

The entire IC is composed of the following blocks.

Crystal Oscillator

HTML5 Icon
Fig. 3: Crystal Oscillator Circuit
      The off chip crystal resonates at 32.768kHz and along with 2 decoupling capacitances it is connected with the internal chip inverter with an input and an output pin. The input pin connect to the inverter input and the output is connected to the inverter output. The output is then fed to a buffer which includes two skewed inverters in order to guarantee oscillation.
      The on-chip oscillator has a first inverter stage to initiate oscillation and a skewed 2-inverter buffer to further escalate the oscillation between power and ground. The 1st inverter stage has pull-up pfet that is twice the pull-down nfet and the 2nd inverter has the inverse configuration.

HTML5 Icon
Fig. 4: Crystal Oscillator Simulations

Clock Select Stage

The clock select stage is a 2x1 multiplexer that selects between the 32.768kHz signal from the crystal oscillator and the 32.768kHz signal from an external frequency generator.

Frequency divider chain

HTML5 Icon
Fig. 5: Division by 2

The frequency divider is a chain of 15 D-Flip-Flops with reset. Each stage is configured so as to produce a division by 2 in the signal frequency. The chain has 2 outputs:

Seconds, Minutes, Hours Counter & Setting Mode

The seconds & minutes counter include a modulo 10 counter and a modulo 6 counter each. These counters are resettable and they count from 0-9 and 0-5 respectively. Between them there is a 2x1 multiplexer that selects between normal mode for the minutes and setting mode for the minutes. The hours counter include a modulo 10 counter and a modulo 3 counter. These counters are resettable and they count from 0-9 and 0-2 respectively. Between the minutes and hours counter there is also a 2x1 multiplexer that selects between normal mode for the minutes and setting mode for the hours.

Display Section

The display section consists of four components:

The multiplexed display driver is a modulo 6 counter. It counts from 0-5 and produces a 3-bit output which is fed to the selectors of the four 6X1 multiplexers.
HTML5 Icon
Fig. 6: Modulo 6 counter

The muxes take in the output of the counters in the way that is illustrated below.

HTML5 Icon
Fig. 7: Multiplexed Display Circuitry

The 4-7 decoder decodes the binary numbers into the decimal 7-segment display based on the truth table below. It connects to the LED digits on the PCB.

HTML5 Icon
Fig. 8: 7-segment decoding truth table

The 3-6 Decoder converts the 3-bit numbers into a 6-bit on-hot output. This way the bit that is 1 will light up the respective LED display at a frequency of 8/6kHz= 1.333kHz which is sufficient in order to avoid the LED display blinking.

Interface

The chip communicates with the outer world using a DIP-28 pin package. The input pins are the Vdd and gnd, the 2 setting mode pins, the global reset, the oscillator input, the mode selection and the clock selection. The rest are output pins like the 6 enable signal, the 7 segment pins, the oscillator output and the hrs and mins frequencies and the 1Hz test pin which is bidirectional.



Back to top