System Overview

As display resolutions increase, it becomes impractical to simultaneously address every pixel individually. The problem occurs because a display with resolution of n-by-n will have n2 pixels and thus require a number of interconnects and driver pins on the order of n2. Clearly, this becomes unworkable for large displays since packaging constraints typically limit the number of I/O pins on an IC. A common strategy to alleviate this issue is known as passive matrix addressing. This strategy works by connecting the LED matrix such that it is arranged with common row connections (cathodes) and column connections (anodes) as shown in Figure 1, leading to a total of 2n required pins instead of n2. This approach only allows for a single row of the display to be controlled at any one time. However, if the rows are scanned through quickly enough, the entire display appears to be continuously illuminated. In exchange for this increased complexity in the driving strategy we greatly reduce the number of I/O pins required on the IC.

In our case, since we were working with a 68 pin package, we opted for a 20x20 display design. This strategy allowed us to use only 40 I/O pins for controlling the display instead of 400. The remaining 28 pins are reserved for power, instructions, and debugging.

Figure 1 - uLED Array Block Diagram
Figure 2 - uD6350 IC pinout

uD6350 is a microLED display driver IC utilizing the previously described passive matrix addressing scheme. It is designed to supply sufficiently high current to properly bias modern phosphide or nitride LED displays. The IC runs on a 2.5V DC supply and supports a 20x20 LED matrix at a refresh rate of 3.125 kHz with 1 MHz serial clock input. It takes 20x20 pixel data via 32 bit serially entered instructions which are input at the 1 MHz serial clock frequency. The IC also has PWM drive capability for adjusting brightness and has a variable refresh rate set by the input clock frequency. The IC is packaged in 68 pin PLCC68 packaging. Figure 2 shows the pinout and pin labels of the IC.

Figure 3 - uD6350 System Block Diagram
Figure 4 - uD6350 test setup

The components of uD6350 are shown in the System Block Diagram in Figure 3. Figure 4 shows uD6350 in its test enviornment, including the microcontroller for sending instructions and the display being driven by uD6350. During power up, the counters and flip-flops in the SCAN and PWM generator need to be initialized. For this, the RST (reset) pin needs to be set low during power up. After supplying the clock via the SCLK, RST needs to be set high. There is no timing requirement for the RST signal so it can be set at any time while the SCLK clock is running. After RST is set, the SCAN and PWM generator will start to run after 3 SCLK clock cycles.

Moreover, the entire IC runs with a clock supplied from the SCLK pin. However, the clock for scan generation can be supplied from CLK2 by setting CLK2_SEL high. This can be used for debugging the IC or to decouple the display scanning and instruction transfer speed. Furthermore, PWM the generator can be completely bypassed by setting PWM_EN pinout low.

The 32-bit instruction is pushed serially into the IC using SCLK, SDI and SLAT pins. The instruction format for the serial data is shown in Figure 5. See Evaluation Board section for instruction timing diagram.

Figure 5 - Instruction format

Figure 6 demonstrates the line scanning behavior of the chip by showing it operating at varying frequency. In this figure, the clock frequency is increased from 10 Hz to 10 MHz and we can observe how when the frequency is low, we see individual lines of the display lighting up. As the clock frequency increases, we start to see a shimmering image, and then finally a consistent image when the frequency goes above 10 kHz.

Figure 6 - Demo LED matrix scanning


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