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This project was in fulfillment of the Spring 2022 Columbia University course EE6350 VLSI Design Lab, delivered by Professor Peter Kinget. The VLSI Design Lab course primarily focused on exposing students to the entire IC design flow. Students complete each step of the IC development process, including defining the IC's application and specifications, system and transistor level simulations, layout, parasitic extraction, post-layout simulation, tape-out, and testing the completed chip on a PCB.
We are very thankful to Prof. Peter Kinget for providing us with the opportunity to learn the intricacies of a full custom IC Design flow. We thank Apple Inc. for sponsoring the fabrication of the chips with 65 nm TSMC CMOS technology. Many thanks to Dr. Anuranjan Jha for being the liaison to Apple for the course. We are also thankful to the course TAs, Petar Barac, Armagan Dascurcu, Longyi Li, and Ray Xu for guiding us throughout the project. Finally, we would like to thank our classmates for their insightful discussions.