An analog continuous-time 4th-order low pass Butterworth filter was rapidly designed using a Verilog description with standard cells and digital logic automatic place-and-route layout tools delivering excellent results. The fabricated test-chip validated the functionality and performance of the standard-cell-based analog-filter. The proposed approach improves design efficiency at the design description stage and offers a dramatic timesaving for the physical design and layout. In future work, this design flow can enable a more seamless integration of analog and digital functions in mixed-signal designs. The standard-cell based design approach with APR layout generation also offers a solution to overcome the challenges that analog designers will face in highly scaled CMOS processes where extensive layout constraints including gridded layout will make the manual approach overly cumbersome and time consuming.