This amplifier was layout using IBM 180-nm RF CMOS process. It was fabricated in MOSIS foundry and packaged using MOSIS DIP28 package. The layout size is 1500 x 1500 microns. Top-level layout is seen in Fig. 1. The signal enters from the bottom side of the layout and exits from the top. A "+" marker at the top-right is used to indicate the orientation with respect to the package.

chip microscope picturechip microscope picture

Fig. 1: Screenshot of the layout designed in Virtuoso vs. actual die photograph

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