Guidelines for Schematic Editing for Analog & RF Circuits

Nov. 2005

Transistor Symbols

This forces you to think where the body should be connected. For pMOS transistors and nMOS transistors in a separate well the option exist to connect the body to the source. Also if you want to do (manual) substrate noise simulations you need access to the body terminal.

Power Supply and Ground

Power supplies and grounds are circuit nodes like any other nodes. The only thing that sets them apart is that a lot of components are connected to them compared to the number of components connected to signal nodes. Using special symbols inside subcells results in a lot of implicit connections that cannot be undone and are hard to trace. Moreover you cannot do any power supply or ground noise simulations on individual blocks or subsections of your circuit. In the layout the supplies and ground are actual nodes. To model the physical reality you often need to include series resistance and inductance or decoupling capacitance at different locations. This is not possible if everything is globally connected through special symbols.

Naming and Connections by Naming

Global nodes have the same problems as outlined above for power supplies and ground. Global nodes do not physically exist. Also connections in schematics made by giving the nets the same name are very difficult to trace. Changes to the schematic might overlook these connections. Connections by naming can simplify the look of a schematic compared to a jungle of wires, but that is deception. If the circuit requires complicated routing, that should be obvious from the schematic.

Hierarchy and Symbols

Pin Placement

Signal Flow

Full Chip Schematics and Simulation


Feel free to contact me with any suggestions for changes. This page is (and will probably remain) work in progress. Graphics would be a nice addition. If you have any you are willing to share, please send them. Thanks. -- PK