Office Hours: TBD

Teaching Assistant: TBD


Course Topics
(subject to change, under development)

The course will focus on both circuits and systems aspects of PLLs since successful PLL design requires a good understanding of the design aspects at both levels.

The course is self-contained but will assume an exposure to basic PLL concepts and building blocks. The introductory material will be covered at a relatively high pace to leave time for more advanced topics.

Note: topics will not necessarily be covered in the order listed here.

Students will be assigned (research) papers on a particular topic to read and present in class.

An extensive project is an integral part of the course. They will be asked to demonstrate the used concepts or circuits in simulation and to present their project to the class.

Design tools

Computer-aided analysis techniques are extensively used. The latest industry-grade CAD tools and simulation tools (Cadence Spectre transistor levels simulations and analog VHDL, and Matlab) are used in this class. See the Design Tools page.

Verilog-A modeling of PLL building blocks will be covered in the class. No prior Verilog-A modeling experience is required.


The course is based on a combination of instructor's notes, technical papers and textbook chapters.

 (Subject to change)
 Class presentation of research paper(s)  1/3
 Design Project and Class presentation  1/3
 Midterm (written) 1/3