NOTES

The username/password to get access to these notes will be handed out at the beginning of the semester.

CAVEAT: These handouts do not necessarily cover all the material of the course. Make sure to complement them with your own class notes. Also, please inform the instructor of any errors you find in the notes.

Notes are under development

Introduction

Integer-N PLLs

Verilog-A Modeling

Fractional-N PLLs

Transistor Level PLL Design

All Digital PLLs

Student Presentations

Project Presentations