NOTES
The username/password to get access to these notes will be handed out at the beginning of the semester.
CAVEAT: These handouts do not necessarily cover all the material of the course. Make sure to complement them with your own class notes. Also, please inform the instructor of any errors you find in the notes.
Notes are under development
Introduction
Integer-N PLLs
- Basics I (pdf)
- Basics II (pdf)
Updated: 2010-01-31 - Basics III -- Noise (pdf)
Verilog-A Modeling
Fractional-N PLLs
Transistor Level PLL Design
All Digital PLLs
Student Presentations
- PLL Figures of Merit [Karthik] (pdf)
- Delay Locked Loops [Noah ] (pdf)
- Phase Noise Measurements [Dinesh] (pdf)
- Advanced Analog PLLs [Chun Wei] (pdf)
- mmWave PLLs [Chen Chia] (pdf)
- Ring Oscillator All Digital PLL [Paul] (pdf)
- TDC with Time Amplifier [Jayanth] (pdf)
- Subsampling based PLLs [Baradwaj] (pdf)
- Jitter Analysis [Jahnavi] (pdf)
Project Presentations
- ADC based TDC [Karthik] (pdf)
- Frequency Locked Loop [Baradwaj] (pdf)
- Inj. locked Divider [Chen Chia](pdf)
- Voltage Regulated PLL (pdf)
- Nonlinear Control for Switching Systems [Noah] (pdf)
- Sampling PLL Techniques [Chun Wei] (pdf)
- Subharmonic Injection Locking [Jahnavi] (pdf)
- Sampling PLL Techniques [Dinesh] (pdf)
- Low Jitter Clock Distribution [Jayanth] (pdf)