EE6350 VLSI Design Lab

DIGITAL CLOCK

Srinidhi Srinivasan   Georgios Charitos

IC Layout

For schematic and layout design we used Cadence Virtuoso CAD software, licensed to Columbia University.

Fig. 9: Basic Cells - Finite basis of our design
We used CMOS VLSI technology and the basic cells - finite basis set we used for our schematic and layout were:

• INV
• 2NAND
• TRANSMISSION GATE

In order to accommodate the very high rise and fall times of the signals, we used long transistors. The minimum length we selected was 2um.

Fig. 10: D Flip Flop with reset schematic


Fig. 11: D Flip Flop with reset layout


Fig. 12: Frequency divider chain schematic


Fig. 13: Frequency divider chain layout


Fig. 14: Modulo 10 counter schematic


Fig. 15: Modulo 10 counter layout


Fig. 16: 2x1 MUX Layout


Fig. 17: 6x1 MUX Layout



Fig. 18: 3x6 Decoder Layout



Fig. 19: 4x7 Decoder Layout



Fig. 20: Chip Schematic



Fig. 21: Chip Symbol




Fig. 22: Final Chip Layout

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© Srinidhi Srinivasan, Georgios Charitos and Columbia University
Last modified on 2016/11/30 23:26:44