Profs. Krishnaswamy, Zhong (IEOR), and Zussman Receive NSF Grant for a Project Focusing on Cross Layering in Full Duplex Wireless
Professors Harish Krishnaswamy, Yuan Zhong (IEOR), and Gil Zussman received a grant from the NSF Enhancing Access to the Radio Spectrum (EARS) program. The $600K grant will support the project "Cross Layering in Full Duplex - from Integrated Circuits to Networking," which is part of the interdisciplinary FlexICoN Project at Columbia University.
The project is motivated by the exponential growth of wireless traffic calls for the design of spectrum-efficient communication schemes. Existing wireless systems are half-duplex, where the separation of a users transmitted and received signal in either frequency or time causes inefficient utilization of the limited spectrum. An emerging and transformative communication technology that can substantially improve spectrum efficiency is Full-Duplex communication, namely, simultaneous transmission and reception on the same frequency channel. The fundamental challenge associated with Full-Duplex communication, however, is the extremely powerful transmitter self-interference, or echo, that can overwhelm the receiver. Full-Duplex operation, therefore, requires the cancellation of the self-interference at the receivers. Despite recent progress in the development of laboratory bench-top Full-Duplex transceiver implementations, these designs utilize bulky off-the-shelf components and are not suitable for compact Integrated Circuit implementations necessary for commercial small-form-factor mobile applications. Moreover, fully utilizing the benefits of Full-Duplex communication calls for a fundamental redesign of the higher layer protocols.
This interdisciplinary project directly addresses the important cross-layer challenges stemming from the need to design compact Full-Duplex transceiver Integrated Circuits and to jointly design the Medium Access Control and Physical layers, while taking into account the Full-Duplex Integrated Circuit characteristics. In particular, a main component of the project is the development of next-generation Full-Duplex transceiver Integrated Circuits that meet the challenging requirements. Another major component is obtaining fundamental understanding of the impact of Full-Duplex Integrated Circuit transceivers, designed for small form factor nodes, on algorithm and Medium Access Control layer design as well as on network capacity. Hence, the main activities include: (i) developing new Full-Duplex transceiver concepts and Integrated Circuits that simultaneously achieve self interference cancellation and robustness to the new interference mechanisms that arise from widely-deployed Full Duplex operation, (ii) deriving realistic models for recently developed Full-Duplex canceller Integrated Circuits and developing adaptive algorithms for physical layer cancellation, (iii) developing algorithms for power control, channel allocation, and scheduling, and studying the resulting Full-Duplex capacity gains (under realistic models), and (iv) understanding the design considerations of Full-Duplex Medium Access Control protocols for random access networks (e.g., Wi-Fi) and for small-cell cellular networks. The developed algorithms will have a strong theoretical foundation and will be evaluated in a unique software-defined Full-Duplex testbed composed of the custom-designed Full-Duplex transceivers developed within the project.
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