On this page we list relevant chapters and sections from some of the reference texts.

We do not necessarily cover all the material in detail; some of the material listed will only be reviewed.

The material is also not covered in the same order. This is just for your information and reference.

Only the material explicitely covered or assigned in class is mandatory.

From Tsividis: Mixed Analog Digital VLSI Devices and Technology

Chapter 2 The MOSFET: Introduction and Qualitative View
MOS Transistor Structure
Assumptions about Terminal Voltages, Currents, and Temperature
A Qualitative Description of MOSFET Operation
Effect of VGS: Level of Inversion
Effect of VSB: The Body Effect
Effect of VDS: Drain Current
Complete Set of Characteristics
Form of Functional ID-VGS Dependence: Practical Limits for Regions of Inversion
Factors Affecting the Extrapolated Threshold Voltage
Other Factors Affecting the Drain Current

Chapter 3 MOSFET DC Modeling
DC Model for Weak and for Strong Inversion
The Current Equations
Model Parameters Influenced by the Body Effect
Origin and Validity of the Model
Drain versus Source
Symmetric Models
General Models and Moderate Inversion
Mobility Dependence on Gate and Substrate Bias
Small-Dimension Effects
The pMOS Transistor
Device Symbols

Chapter 4 MOSFET Small-Signal Modeling
Small-Signal Conductance Parameters
Expressions for Small-Signal Conductance Parameters in Weak and in Strong Inversion
Gate Transconductance
Body Transconductance
Drain-Source Conductance
Drain-Substrate Conductance
Small-Signal Parameters in the Presence of Second-Order Effects
Capacitance Parameters
Extrinsic Capacitances
Intrinsic Capacitances in Weak and in Strong Inversion
Intrinsic Cutoff Frequency and Limits of Model Validity
Extrinsic Parasitic Resistances


A CAD methodology for optimizing transistor current and sizing in analog CMOS design
Binkley, D.M.; Hopper, C.E.; Tucker, S.D.; Moss, B.C.; Rochelle, J.M.; Foty, D.P.;
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , Volume: 22 , Issue: 2 , Feb. 2003 Pages:225 - 237

IEEE Journal Papers can be downloaded from the http://ieeexplore.ieee.org website from an on campus computer.


D. M. Binkley, B. J. Blalock and J. M. Rochelle, Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design, Journal Analog Integrated Circuits and Signal Processing, Volume 47, Number 2, pp. 137-163, May 2006.

From Razavi: Design of Analog CMOS Integrated Circuits

3 Single-Stage Amplifiers (Review)
3.1 Basic Concepts
3.2 Common-Source Stage
3.2.1 Common-Source Stage with Resistive Load
3.2.2 CS Stage with Diode-Connected Load
3.2.3 CS Stage with Current-Source Load
3.2.4 CS Stage with Triode Load
3.2.5 CS Stage with Source Degeneration
3.3 Source Follower
3.4 Common-Gate Stage
3.5 Cascode Stage
3.5.1 Folded Cascode

4 Differential Amplifiers (Review)
4.1 Single-Ended and Differential Operation.
4.2 Basic Differential Pair
4.2.1 Qualitative Analysis
4.2.2 Quantitative Analysis
4.3 Common-Mode Response
4.4 Differential Pair with MOS Loads

5 Passive and Active Current Mirrors (Review)
5.1 Basic Current Mirrors
5.2 Cascode Current Mirrors
5.3 Active Current Mirrors
5.3.1 Large-Signal Analysis
5.3.2 Small-Signal Analysis
5.3.3 Common-Mode Properties

6 Frequency Response of Amplifiers (Review)
6.1 General Considerations
6.1.1 Miller Effect
6.1.2 Association of Poles with Nodes
6.2 Common-Source Stage
6.3 Source Followers
6.4 Common-Gate Stage
6.5 Cascode Stage
6.6 Differential Pair

7 Noise
7.1 Statistical Characteristics of Noise
7.1.1 Noise Spectrum
7.1.2 Amplitude Distribution
7.1.3 Correlated and Uncorrelated Sources
7.2 Types of Noise
7.2.1 Thermal Noise
7.2.2 Flicker Noise
7.3 Representation of Noise in Circuits
7.4 Noise in Single-Stage Amplifiers
7.4.1 Common-Source Stage
7.4.2 Common-Gate Stage
7.4.3 Source Followers
7.4.4 Cascode Stage
7.5 Noise in Differential Pairs
7.6 Noise Bandwidth

9 Operational Amplifiers
9.1 General Considerations
9.1.1 Performance Parameters
9.2 One-Stage Op Amps
9.3 Two-Stage Op Amps
9.4 Gain Boosting
9.5 Comparison
9.6 Common-Mode Feedback
9.7 Input Range Limitations
9.8 Slew Rate
9.10 Noise in Op Amps

10 Stability and Frequency Compensation
10.1 General Considerations
10.2 Multipole Systems
10.3 Phase Margin
10.4 Frequency Compensation
10.5 Compensation of Two-Stage Op Amps
10.5.1 Slewing in Two-Stage Op Amps
10.6 Other Compensation Techniques

11 Bandgap References
11.1 General Considerations
11.2 Supply-Independent Biasing
11.3 Temperature-Independent References
11.3.1 Negative-TC Voltage
11.3.2 Positive-TC Voltage
11.3.3 Bandgap Reference
11.4 PTAT Current Generation
11.5 Constant-Gm Biasing
11.6 Speed and Noise Issues
11.7 Case Study

12 Introduction to Switched-Capacitor Circuits
12.1 General Considerations
12.2 Sampling Switches
12.2.1 MOSFETS as Switches
12.2.2 Speed Considerations
12.2.3 Precision Considerations
12.2.4 Charge Injection Cancellation
12.3 Switched-Capacitor Amplifiers 12.3.2 Noninverting Amplifier