In this project, we explore new algorithm, architecture, and circuits to enable neuromorphic computing with limited resources. In one project we are interested in recycling on-chip data storage so as to train a deep neural network having as many as synaptic weights on a chip without excessive accesses of off-chip data storage (DRAM or FLASH) which incur 3-4 orders of magnitude worse delay and power. In a different project, we are interested in monitoring the progress of training and learning without lengthy test data based verification. We also explored emerging neural network architecture such as Spiking Neural Network (SNN). In a project, we devised a new algorithm is more suitable to such new architecture and hardware. We are also interested in online continual learning and training of deep neural networks.

Related publications: ISLPED15, VLSI-SoC15, arXiv15, VLSI16, NC16, DATE17, Arxiv17, Arxiv17

In this project, we explore cross-layer design for enabling machine-learning and DSP capability in embedded systems with limited computing and memory resources. One of our focus areas is the Brain Machine Interface (BMI) where on-chip unsupervised and supervised clustering and intention decoding are highly demanded for building user-specific models. This can improve the accuracy of local decision and also reduce wireless communication data rate. We have demonstrated some of the best hardware that can achieve a record energy efficiency.

Related publications: DAC15, VLSI16, ISOCC16, TCASI16, DATE17, MICRO17, ESSCIRC17

In this project, we combine analog and digital computing hardware to tackle most computationally-intensive tasks. We take advantage the superiority of analog hardware in computing for approximate results. For solving differential equations and linear algebra, analog hardware can provide initial approximate solutions rapidly and very efficiently, which digital hardware then refine without convergence issue. For machine-learning, we can use analog hardware to accerelate computing where imprecise results can be tolerated.

Related Publications: ESSCIRC15, JSSC16, ISCA16, MICRO-Magazine17, MICRO17

In this project, we are seeking on designing a low-drop-out regulator based on event-driven control systems. Such unconventional control systems can break the trade-off among latency, number of samples, and power dissipation of the very conventional Nyquist-rate time-driven control systems. Thanks to the event-driven scheme, our LDOs can use a small, full-integrated output capacitor at high conversion efficiency.

Related publications: ISSCC16, ISSCC17, ISLPED17, JSSC17

In this project, we investigate new techniques on in-situ Error Detection And Correction (EDAC) and Dynamic Voltage Frequency Scaling (DVFS) to ensure robustness and energy-efficiency in emerging circuits and architectures including micro and sub-microwatt circuits and non Von-Neumann architecture. Existing EDAC and DVFS have focused on more conventional systems and are not suitable to those emerging systems. We demonstrated such EDAC and DVFS techniques at the minimal hardware overhead.

Related publications: JETCAS11, ISLPED12, VLSI14, ISLPED14, JSSC15, VLSI16, ASSCC16, VLSI16, TVLSI16, JSSC17, ESSCIRC17

Today's high-performance microprocessors are thermally-limited. This mandates most of them to employ Dynamic Thermal Management (DTM), where thermal sensors are embedded at multiple locations of a microprocessor and monitor temperatures that are used to manage the operation of the microprocessor under local and global thermal constraints. While existing sensors achieve impressive area and accuracy, emerging technology trends such as multi-core architectures, 3D-integration, tri-gate devices, and low-voltage operation demand the development of even better sensors having harder requirements to meet such as compact footprint and voltage-scalability down to near-threshold regime. In this project, we explore both system and circuits for new DTM. We studied the new requirements of sensor circuits for improving accuracy of DTM, and demonsrated ultra-compact and voltage scalable sensors that meet those requirement.

Related publications: ISSCC14, CICC15, JSSC15, CICC17, ISLPED17, MWSCAS17

In this project, we investigate new techniques that enable accurate in-situ aging monitoring even under large environmental variations (e.g., temperature) for embedded SRAM. We also develop framework and algorithm that can extract circuit and architecture level information such as Data Retention Voltage of SRAM arrays from low-level measurement. This monitoring ability is foundational for dynamic reliability management frameworks, which can maximize the performance and energy-efficiency under a reliability envelope without imposing worst-case margin.

Related publications: DAC14, ISSCC15, ESSCIRC16

Concerns on security in connected and mobile devices are ever-growing. In this project, we explored hardware design for important security functions such as Physically Unclonable Function (PUF), where we have demonstrated among the most compact and the most robust circuits against process, voltage, temperature variations and long-term device wearout.

Related publications: VLSI15, JSSC16, US-Patent16, ISCAS17, CICC17

As we scale voltage to near and sub-threshold regime, digital CMOS circuits reach the limit of energy-efficiency improvement due to the exponentially growing contribution of active leakage dissipation. In this regard, active leakage poses the practical limit of energy-efficiency. We are interested in suppressing this active leakage and thus aim to push the limit of energy-efficiency via voltage scaling. We explored the role of deep pipelining and massive parallelism, and came up with pipelining strategies for active-leakage dominated circuits. We also explored temporally and spatially fine-grained leakage suppression technique for always-on blocks.

Related publications: ISSCC11, ISLPED10, DAC11, JSSC12, ICICDT12, TCASII12, S3S13, ISLPED14, ICCD15, TVLSI16, ESSCIRC17

We are interested in desiging a power management system for ultra-low power microsystems, which typically consists of regulators, references, switching converters, batteries, energy-storage capacitors, etc. The goal is to make those building blocks ultra energy-efficient so as to maximize the conversion efficiency from energy sources to load systems. In one project, we demonstrated picowatt voltage reference circuits that is 3-4 orders of magtnidues more power efficient than previous state of the arts. Another focus is to make it, particularly passive elements such as capacitors, to be compact sufficiently for complete on-chip integration. Finally, we also focus on managing energy conversion processes among those building blocks to maximize energy efficiency against varitions in and mismatches between harvesting and consumption.

Related publications: VLSI09, CICC09, ESSCIRC10, JSSC12, ASSCC16, JSSC17

The project developed a 1$mm^3$ system that consumes ultra low power in both active and standby modes for sensor applications. The system includes CPU, SRAM, ROM, a power management unitand a watchdog timer. To achieve extremely low power consumption we investigate 1) the system-level optimization, including technology selection 2) power gating switch design schemes for pico-watt standby power consumption 3) 7fW/cell retentive SRAM arrays 4) designing robust ultra-low voltage ROM arrays 5) performing top-level integration. The whole system consumes record 30pW during standby mode and 300nW during active mode. This work is featured in MIT Technology Review and EE Times. It is also listed as one of the notable innovations in the ”The Year in Computing 2008” of the MIT Technology Review. Second and third generations of the Phoenix Processor are also demonstrated.

Related publications: VLSI08, ISLPED08, CICC08, ESSCIRC08, IEDM08, DAC/ISSCC Design Contest 09, JSSC09, TVLSI11, ISSCC10, ISSCC11, ISCAS11, JSSC13, TCASI13, TCASII13