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The EE6350 VLSI Design Lab is a graduate course that focuses on the
design, simulation, layout, verification and tape-out of an IC
design in the spring. An industrial sponsor is
sponsoring the fabrication of the chips in a 65nm CMOS foundry
technology. During summer, the foundry fabricates the chips that students
subsequently test in the fall.
YouTube Channel
Students make a video presentation demonstrating the operation of their
chip and describing the design details. Please visit our
YouTube channel or the class linked in the
header.
Search Projects
The project webpages documenting the student designs are posted on
the yearly class webpages linked in the header above; they contain a
wealth of chip design information that you can search.