0.5 V Analog integrated circuits for nanoscale CMOS technologies.

Peter Kinget

Columbia University, New York, NY, USA
  
Semiconductor technology scaling a.k.a. 'Moore's Law' has enabled
function density increases and cost reductions by orders of magnitudes,
but for shrinking device sizes the operating voltages have to be
reduced. As we move into the nanoscale semiconductor technologies, power
supply voltages well below 1 V are projected. The design of MOS analog
circuits operating from a power supply voltage of 0.5 V is discussed in
this talk. The scaling of traditional circuit topologies is not possible
anymore and new circuit topologies and biasing strategies have to
developed. Several design examples are presented. The circuit
implementations of gate and body-input 0.5~V operational
transconductance amplifiers and their robust biasing are discussed.
These building blocks are combined for the realization of active
varactor-tuned RC filters operating from 0.5 V using standard devices
with a |VT| of 0.5 V in a standard 0.18 um CMOS technology. Work done in
collaboration with Shouri Chatterjee and Yannis Tsividis.