If you haven't read the CAD tool information page, READ THAT FIRST.

An important part of getting accurate pre-layout simulation is accurately predicting the layout parasitics associated with the source and drain diffusions.  As we know, the parasitic capacitance associated with the diffusions is not trivial and can be a significant part of the gate loading, particularly in low fan-out situations.  To get getter pre-layout simulation accuracy, we have a set-up in which the transistors in the schematic have a "layout type" from which the appropriate AS, AD, PS, and PD parameters for SPICE are determined.  You should choose device types based on how you know the diffusions will be shared.  The device types contain two letters -- the first letter corresponds to the nature of the diffusion on the source and the second letter corresponds to the nature of the diffusion on the drain.  These letters are coded as follows:

• c.  Fully-contacted diffusion that does not abut another diffusion.
• e.  Fully-contacted diffusion that must be shared with an n contact.
• n.  Non-contacted diffusion.  This must be shared with an e or s contact.
• s.  Non-contacted diffusion that must be shared with an n contact.