9/8

Introduction, non-decimal number systems, decimal and alphanumeric codes. Binary logic and gates.

1, 2.1

9/13

Boolean algebra.

2.2

9/15

Standard forms.

2.3

9/20

Map simplification.

2.4

9/22

Map manipulation.

2.5

9/27

NAND and NOR Gates, XOR Gates.

2.6�2.7

9/29

IC Families, CMOS.

2.8�2.9

10/4

Combinational circuits, analysis and design procedures, decoders.

3.1�3.5

10/6

Encoders,  multiplexers.

3.6�3.7

10/11

Binary adders, binary subtraction.

3.8�3.9

10/13

Binary adder-subtractors, multipliers.

3.10-3.11

10/18

- No Class -

10/20

Introduction to sequential circuits. Latches.

4.1�4.2

10/22

Flip-flops: master-slave, edge-triggered. Characteristic tables.

4.3

Sequential circuit analysis.

4.4

10/25

- No Class -

10/27

- No Class -

11/1

Academic Holiday � no class

11/3

- No Class -

11/8

Sequential circuit design. Design using D and JK flip-flops.

4.5�4.7

11/10

Midterm

11/15

Registers, shift registers, ripple counter.

5.1�5.4

11/17

Synchronous binary counters. Other counters.

5.5�5.7

11/22

RAM, ECC RAM

6.1�6.5

11/24

PLA, PAL, VLSI Programmable logic devices.

6.6�6.10

11/29

Datapaths and operations. Register transfer operations, microoperations. Multiplexer and bus-based transfer. Datapaths.

7.1�7.6

12/1

The ALU, shifter, control word, pipelining.

7.7�7.12

12/6

Control unit. Algorithmic state machines. Design example: binary multiplier.

8.1�8.3

12/8

Binary multiplier with hardwired and microprogrammed control.

8.4�.5

12/10

A simple computer architecture. Single cycle hardwired control. Multiple cycle microprogrammed control, pipelining.

8.6�8.9

Instruction set architecture.

9.1�9.3

12/13

Special Topics - Review

12/20

Final