Date

Material

Reading

9/3

Introduction, non-decimal number systems, decimal and alphanumeric codes. Binary logic and gates.

1, 2.1

9/8

Boolean algebra.

2.2

9/10

Standard forms.

2.3

9/15

Map simplification.

2.4

9/17

Map manipulation.

2.5

9/22

NAND and NOR Gates, XOR Gates, IC Families, CMOS.

2.6�2.9

9/24

Combinational circuits, analysis and design procedures.

3.1�3.4

9/29

Decoders, encoders, multiplexers.

3.5�3.7

10/1

Binary adders, subtraction, adder-subtractors

3.8�3.13

10/6

Multipliers, decimal arithmetic, standard graphics symbols.

3.11�3.13

10/8

Introduction to sequential circuits. Latches

4.1�4.2

10/13

Flip-flops: master-slave, edge-triggered. Characteristic tables.

4.3

10/15

Sequential circuit analysis.

4.4

10/20

Sequential circuit design. Design using D and JK flip-flops.

4.5�4.7

10/22

Midterm (moved to 10/29)

10/27

Registers, shift registers, ripple counter.

5.1�5.4

10/29

Synchronous binary counters. Other counters.

5.5�5.7

11/3

Academic Holiday

11/5

RAM, ECC RAM

6.1�6.5

11/10

PLA, PAL, VLSI Programmable logic devices.

6.6�6.10

11/12

Datapaths and operations. Register transfer operations, microoperations. Multiplexer and bus-based transfer. Datapaths.

7.1�7.6

11/17

The ALU, shifter, control word, pipelining.

7.7�7.12

11/19

Control unit. Algorithmic state machines. Design example: binary multiplier.

8.1�8.3

11/24

Binary multiplier with hardwired and microprogrammed control.

8.4�.5

11/26

Thanksgiving Day

12/1

A simple computer architecture. Single cycle hardwired control. Multiple cycle microprogrammed control, pipelining.

8.6�8.9

12/3

Instruction set architecture (1).

9.1�9.3

12/8

Instruction set architecture (2).

9.4�9.7

12/??

Final