Date: March 25, 2020
Speaker: Gage Hills
Faculty host: Prof. Harish Krishnaswamy
Abstract: At the exact moment when next-generation applications promise to revolutionize every aspect of our lives, progress in computing is stalling. Unfortunately, conventional approaches for improving electronics (transistor scaling, specialized accelerators, etc.) are yielding diminishing returns. This is igniting an increasingly rich set of new research directions, including new physics, nanomaterials, devices, memories, systems, architectures, and integration techniques. Yet such a promising – and overwhelming – set of options raises critical questions:
Which technology, or combination of technologies, gives the best “bang for the buck”?
How will new technology capabilities change the way that we design systems?
How can we practically realize these new system designs using new nanotechnologies, given the major imperfections inherent to these emerging technologies?
In this talk, I will present my work on answering these questions through the new discipline of emerging nano-design: discovering and developing new circuits, systems, and design methodologies that leverage the unique benefits of new technologies, while simultaneously overcoming their inherent challenges. Rather than focusing on isolated improvements in devices, circuits, or architectures, I will show that by combining interactions between technologies across the computing stack, we can achieve far-larger benefits overall.
As a case study in emerging nano-design, I will discuss my work on realizing a future path for energy-efficient very-large-scale integrated (VLSI) computing systems leveraging carbon nanotube (CNT) field-effect transistors (CNFETs). While CNTs were a scientifically-interesting nanomaterial, their benefits for realistic VLSI circuits were not well understood, and major defects and variations inherent to CNTs had prevented large-scale CNFET circuits from being realized. I will present an end-to-end framework for quantifying new technology benefits that uses detailed physical designs to account for important effects in realistic VLSI circuits. Using this framework, I will show that CNFETs offer major energy efficiency benefits for sub-10 nm node digital VLSI systems. Moreover, to realize a practical path for building such future systems, I will describe and experimentally validate new emerging nano-design techniques for overcoming the major defects and variations inherent to CNTs. By leveraging these works, my collaborators and I have realized the most complex nanoelectronic system fabricated from any beyond-silicon emerging nanotechnology: a 16-bit microprocessor built entirely out of CNFETs. Beyond specific CNT technologies, I will also present my work on realizing new three-dimensional architectures that integrate multiple nanotechnologies to achieve even higher degrees of energy efficiency for emerging data-intensive applications.
I will conclude by describing how emerging nano-design is now enabling the transition of these nanotechnologies and systems from academic “labs” to commercial “fabs”. While the technologies and systems described represent one promising direction for next-generation electronics, emerging nano-design can (and should) be expanded to analyze, enable, and realize an increasingly diverse range of technologies for an increasingly diverse set of future systems and applications.
Bio: Gage Hills received his PhD in Electrical Engineering at Stanford University under the supervision of Professor Subhasish Mitra and co-advised by Professor H.-S. Philip Wong. He is currently a Postdoctoral Associate in the department of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology (MIT), working in the Novel Electronic Systems group led by Professor Max Shulaker. Gage’s current research interests are in the broad area of emerging nano-design. His research results include new design methodologies for overcoming variations in emerging nanotechnologies (which have now been commercially adopted), the most advanced nanoelectronic system fabricated from emerging nanotechnologies (a modern RISC-V microprocessor, highlighted in Nature 2019), an end-to-end framework for quantifying system-level benefits of new technologies (demonstrating that CNFETs offer major energy efficiency benefits for sub-10 nm node circuits even in the presence of substantial variations, in collaboration with imec and TSMC), and leading the nano-design effort in the DARPA Three-Dimensional System-on-Chip (3DSoC) program. Gage also enjoys teaching and has been a guest lecturer in several classes at Stanford and MIT.
Event Contact: Eliese Lissner | email@example.com