In this project, we investigate a design approach for upgrading the resiliency of ultra-low-voltage (ULV) microprocessors through a voltage-scalable and low-overhead in-situ error detection and correction (EDAC) technique. Particular efforts are made to overcome the poor voltage scalability and area/energy/throughput overhead of the existing EDAC techniques when applied to ULV designs. We demonstrate the first EDAC technique that works at near- and sub-threshold regime. Applied onto a microprocessor, it can remove the worst-case margin, a major problem in near and sub-threshold design, at the minimal area overhead of 8.2%
In this project, we investigate new techniques that enable accurate in-situ aging monitoring even under large environmental variations (e.g., temperature) for both pipeline and SRAM. This monitoring ability is foundational for dynamic reliability management frameworks, which can maximize the performance and energy-efficiency under a reliability envelope without imposing worst-case margin. Our technique for pipeline achieves highly-accurate monitoring with an error of 15.5% across the temperature variations in self-test phases from 0°C to 80°C, exhibiting >30× improvement in accuracy as compared to the conventional technique. We also develop techniques for SRAM, to be presented in 2015 ISSCC.
On-chip temperature sensors are key for the thermal management of multi-core microprocessors. The sensors are embedded at multiple locations of a microprocessor and monitor temperatures that are used to manage the operation of the microprocessor under local and global thermal constraints. While existing sensors achieve impressive area and accuracy, emerging technology trends such as multi-core architectures, 3D-integration, tri-gate devices, and low-voltage operation demand the development of even better sensors having harder requirements to meet such as compact footprint and voltage-scalability down to near-threshold regime. We design and demonstrate the sensor that is the smallest (115 to 279um2) and the most voltage scalable (down to 0.6V) while meeting required accuracy after one-point temperature calibration.
Related publications: ISSCC14,
In the project, we develope a FFT core that consumes 17.7nJ/1024-pt complex FFT at 30MHz clock frequency at Vdd=0.27V by using architecture and circuit-level techniques. This demonstrates the lowest energy consumption per FFT operation. Our contributions include 1) investigating energy-optimal, yet fast pipelining schemes in ultra-low voltage regimes in order to design multipliers, adders, and butterfly networks 2) investigating latch-based pipelining to mitigate process variations between pipelined stages 3) designing a robust clock network in ultra low voltage regimes 4) performing top-level integration.
The project developed a power system, including a linear regulator, voltage references, and switched capacitor networks for delivering nano-amphere current at sub or near-threshold supply voltage. We investigate 1) designing an ultra-low power voltage reference to provide constant voltage against temperature and power source output with 2.2 pico-watt power consumption, (which is 3-4 orders of magnitude lower than previous state-of-the-arts) 2) analyzing the variability of the ultra-low power voltage refernece in three different technologies (65nm,130nm, and 180nm CMOS) 3) designing a digitally trimmable version of the voltage referenece to minimize the spread of temperature sensitivity and output accuracy.
The project developed a 1$mm^3$ system that consumes ultra low power in both active and standby modes for sensor applications. The system includes CPU, SRAM, ROM, a power management unitand a watchdog timer. To achieve extremely low power consumption we investigate 1) the system-level optimization, including technology selection 2) power gating switch design schemes for pico-watt standby power consumption 3) 7fW/cell retentive SRAM arrays 4) designing robust ultra-low voltage ROM arrays 5) performing top-level integration. The whole system consumes record 30pW during standby mode and 300nW during active mode. This work is featured in MIT Technology Review and EE Times. It is also listed as one of the notable innovations in the ”The Year in Computing 2008” of the MIT Technology Review. Second and third generations of the Phoenix Processor are also demonstrated.