Low power VLSI circuit, architecture and system design and methodology
Variation tolerant circuit and system design techniques
Power conversion circuit and system design
Cross-layer hardware design for emerging cyber physical system, ubiquitous computing, and biomedical applications
In our research, we are pushing the limit of performance, energy efficiency and robustness of highly integrated circuits and systems designs, targetting applications ranging from traditional computers to emerging cyber physical systems and biomedical systems. We research novel design techniques and methodologies and verify their effectiveness often through actual hardware (often in the form of integrated circuits) developments and charaterizations. In this page, you can find a few example works where we have demonstrated the best energy-efficient microsystems, power conversion analog circuits, and digital FFT accelerators.
Super-pipelined FFT core in 65nm CMOS
In the project, we develope a FFT core that consumes 17.7nJ/1024-pt complex FFT at 30MHz clock frequency at Vdd=0.27V by using architecture and circuit-level techniques. This demonstrates the lowest energy consumption per FFT operation. Our contributions include 1) investigating energy-optimal, yet fast pipelining schemes in ultra-low voltage regimes in order to design multipliers, adders, and butterfly networks 2) investigating latch-based pipelining to mitigate process variations between pipelined stages 3) designing a robust clock network in ultra low voltage regimes 4) performing top-level integration.
Power system for an ultra-low power micro-system
The project developed a power system, including a linear regulator, voltage references, and switched capacitor networks for delivering nano-amphere current at sub or near-threshold supply voltage. We investigate 1) designing an ultra-low power voltage reference to provide constant voltage against temperature and power source output with 2.2 pico-watt power consumption, (which is 3-4 orders of magnitude lower than previous state-of-the-arts) 2) analyzing the variability of the ultra-low power voltage refernece in three different technologies (65nm,130nm, and 180nm CMOS) 3) designing a digitally trimmable version of the voltage referenece to minimize the spread of temperature sensitivity and output accuracy.
Phoenix Processor, ultra low power system for sensor applications
The project developed a 1$mm^3$ system that consumes ultra low power in both active and standby modes for sensor applications. The system includes CPU, SRAM, ROM, a power management unitand a watchdog timer. To achieve extremely low power consumption we investigate 1) the system-level optimization, including technology selection 2) power gating switch design schemes for pico-watt standby power consumption 3) 7fW/cell retentive SRAM arrays 4) designing robust ultra-low voltage ROM arrays 5) performing top-level integration. The whole system consumes record 30pW during standby mode and 300nW during active mode. This work is featured in MIT Technology Review and EE Times. It is also listed as one of the notable innovations in the ”The Year in Computing 2008” of the MIT Technology Review. Second and third generations of the Phoenix Processor are also demonstrated.
DAC/ISSCC Design Contest 09