Research directions

  • Variation-, themral-, and aging-adaptive VLSI circuit, architecture, and system design

  • Ultra-low-energy microsystem design for biomedical devices, brain-computer-interface, and Internet-of-Things

  • Machine-learning architecture and circuits

  • Non-conventional computing and control systems

In our research, we are pushing the limit of performance, energy efficiency, robustness, and integration of VLSI circuits and systems designs, targetting applications ranging from traditional computers to emerging cyber physical systems and biomedical systems. We research novel design techniques and methodologies and verify their effectiveness often through actual hardware (often in the form of custom ICs) developments and charaterizations.

Non-Conventional Computing, Processing, and Control Systems


In this project, we explore highly non-conventional VLSI systems design for computing, processing, and control. In one project we are pursuing analog computing acclerators to scientific computing workloads such as solving linear/non-linear differential equations, where analog circuits based computing macros can vastly outperform the very conventional digital counterparts by more than two orders of magnitudes at the same accuracy. In other project we are seeking on designing fully event-driven control systems. Such unconventional control systems can break the trade-off among latency, number of samples, and power dissipation of the very conventional Nyquist-rate control systems. We have explored the design of a digital low-drop-out (LDO) regulator based on this novel event-driven control systems. Thanks to the event-driven scheme, our LDO can use a small, full-integrated output capacitor at high current efficiency. As a possible building block, we have also explored asynchronous digital pipelines at very low supply voltages.

Related publications: ASYNC13, ISLPED13, ESSCIRC15, ISSCC16, JSSC16, ISCA16

Machine-learning and inference algorithm and hardware for Resource-Constrained Microsystems


In this project, we explore cross-layer design for enabling machine-learning capability in ultra-low-power microsystems. We develop novel algorithms to extend learning memory capacity, emerging architectures (e.g., spiking neurons), and resource-efficient circuit implementation, to push the boundary of accuracy, throughput, and energy-efficiency. One of our focus areas is the brain machine interface (BMI) where on-chip unsupervised and supervised clustering and classification is highly demanded for individualizing data-processing and reducing wireless communication data rate. We have demonstrated some of the best hardware that can achieve high accuracy yet consume very low power and silicon footprint.

Related publications: DAC15, ISLPED15, VLSI-SoC15, arXiv15, VLSI16, VLSI16, NC16, DATE17, DATE17

Voltage-Scalable, Low-Overhead, Within-a-Cycle, In-Situ Error Detection and Correction


In this project, we investigate a design approach for upgrading the resiliency of ultra-low-voltage (ULV) microprocessors through a voltage-scalable and low-overhead in-situ error detection and correction (EDAC) technique. Particular efforts are made to overcome the poor voltage scalability and area/energy/throughput overhead of the existing EDAC techniques when applied to ULV designs. We demonstrate the first EDAC technique that works at near- and sub-threshold regime. Applied onto a microprocessor, it can remove the worst-case margin, a major problem in near and sub-threshold design, at the minimal area overhead of 8.2%

Related publications: JETCAS11, ISLPED12, VLSI14, ISLPED14, JSSC15, VLSI16, TVLSI16

In-Situ and In-Field Self-Testing Techniques for Device Aging in Pipeline and SRAM


In this project, we investigate new techniques that enable accurate in-situ aging monitoring even under large environmental variations (e.g., temperature) for both pipeline and SRAM. This monitoring ability is foundational for dynamic reliability management frameworks, which can maximize the performance and energy-efficiency under a reliability envelope without imposing worst-case margin. Our technique for pipeline achieves highly-accurate monitoring with an error of 15.5% across the temperature variations in self-test phases from 0°C to 80°C, exhibiting >30× improvement in accuracy as compared to the conventional technique. We also develop techniques for SRAM, to be presented in 2015 ISSCC.

Related publications: DAC14, ISSCC15, ESSCIRC16

Ultra-Compact Temperature Sensor for Dense Thermal Monitoring


On-chip temperature sensors are key for the thermal management of multi-core microprocessors. The sensors are embedded at multiple locations of a microprocessor and monitor temperatures that are used to manage the operation of the microprocessor under local and global thermal constraints. While existing sensors achieve impressive area and accuracy, emerging technology trends such as multi-core architectures, 3D-integration, tri-gate devices, and low-voltage operation demand the development of even better sensors having harder requirements to meet such as compact footprint and voltage-scalability down to near-threshold regime. We design and demonstrate the sensor that is the smallest (115 to 279um2) and the most voltage scalable (down to 0.6V) while meeting required accuracy after one-point temperature calibration.

Related publications: ISSCC14, CICC15, JSSC15

Super-Pipelined FFT Core in 65nm CMOS


In the project, we develope a FFT core that consumes 17.7nJ/1024-pt complex FFT at 30MHz clock frequency at Vdd=0.27V by using architecture and circuit-level techniques. This demonstrates the lowest energy consumption per FFT operation. Our contributions include 1) investigating energy-optimal, yet fast pipelining schemes in ultra-low voltage regimes in order to design multipliers, adders, and butterfly networks 2) investigating latch-based pipelining to mitigate process variations between pipelined stages 3) designing a robust clock network in ultra low voltage regimes 4) performing top-level integration.

Related publications: ISSCC11, ISLPED10, DAC11, JSSC12, ICICDT12, TCASII12, S3S13, ISLPED14

Power system for an Ultra-Low Power Micro-System


The project developed a power system, including a linear regulator, voltage references, and switched capacitor networks for delivering nano-amphere current at sub or near-threshold supply voltage. We investigate 1) designing an ultra-low power voltage reference to provide constant voltage against temperature and power source output with 2.2 pico-watt power consumption, (which is 3-4 orders of magnitude lower than previous state-of-the-arts) 2) analyzing the variability of the ultra-low power voltage refernece in three different technologies (65nm,130nm, and 180nm CMOS) 3) designing a digitally trimmable version of the voltage referenece to minimize the spread of temperature sensitivity and output accuracy.

Related publications: VLSI09, CICC09, ESSCIRC10, JSSC12

Phoenix Processor, Ultra-Low-Power System for Sensor Applications


The project developed a 1$mm^3$ system that consumes ultra low power in both active and standby modes for sensor applications. The system includes CPU, SRAM, ROM, a power management unitand a watchdog timer. To achieve extremely low power consumption we investigate 1) the system-level optimization, including technology selection 2) power gating switch design schemes for pico-watt standby power consumption 3) 7fW/cell retentive SRAM arrays 4) designing robust ultra-low voltage ROM arrays 5) performing top-level integration. The whole system consumes record 30pW during standby mode and 300nW during active mode. This work is featured in MIT Technology Review and EE Times. It is also listed as one of the notable innovations in the ”The Year in Computing 2008” of the MIT Technology Review. Second and third generations of the Phoenix Processor are also demonstrated.

Related publications: VLSI08, ISLPED08, CICC08, ESSCIRC08, IEDM08, DAC/ISSCC Design Contest 09, JSSC09, TVLSI11, ISSCC10, ISSCC11, ISCAS11, JSSC13, TCASI13, TCASII13