
In the project, we develope a FFT core that consumes 17.7nJ/1024pt complex FFT at 30MHz clock frequency at Vdd=0.27V by using architecture and circuitlevel techniques. This demonstrates the lowest energy consumption per FFT operation. Our contributions include 1) investigating energyoptimal, yet fast pipelining schemes in ultralow voltage regimes in order to design multipliers, adders, and butterfly networks 2) investigating latchbased pipelining to mitigate process variations between pipelined stages 3) designing a robust clock network in ultra low voltage regimes 4) performing toplevel integration. Related publications: ISSCC11, ISLPED10, DAC11, JSSC12, ICICDT12 
The project developed a power system, including a linear regulator, voltage references, and switched capacitor networks for delivering nanoamphere current at sub or nearthreshold supply voltage. We investigate 1) designing an ultralow power voltage reference to provide constant voltage against temperature and power source output with 2.2 picowatt power consumption, (which is 34 orders of magnitude lower than previous stateofthearts) 2) analyzing the variability of the ultralow power voltage refernece in three different technologies (65nm,130nm, and 180nm CMOS) 3) designing a digitally trimmable version of the voltage referenece to minimize the spread of temperature sensitivity and output accuracy. 
The project developed a 1$mm^3$ system that consumes ultra low power in both active and standby modes for sensor applications. The system includes CPU, SRAM, ROM, a power management unitand a watchdog timer. To achieve extremely low power consumption we investigate 1) the systemlevel optimization, including technology selection 2) power gating switch design schemes for picowatt standby power consumption 3) 7fW/cell retentive SRAM arrays 4) designing robust ultralow voltage ROM arrays 5) performing toplevel integration. The whole system consumes record 30pW during standby mode and 300nW during active mode. This work is featured in MIT Technology Review and EE Times. It is also listed as one of the notable innovations in the ”The Year in Computing 2008” of the MIT Technology Review. Second and third generations of the Phoenix Processor are also demonstrated. Related publications: VLSI08, ISLPED08, CICC08, ESSCIRC08, IEDM08, DAC/ISSCC Design Contest 09 JSSC09, TVLSI11, ISSCC10, ISSCC11 