Welcome to VLSI Lab at Columbia University. We work on novel design techniques and methodologies for better energy efficiency, performance and robustness of highly integrated circuits and systems. We build and charaterize hardware, often in the form of integrated circuits, like those in the above picture. Please visit our research page and publication list to get a sense of research that we are involved with. We are also collaborating with faculty members in Columbia Integrated Systems Lab, Computer Engineering Program and EE department.

July, 2018: Teng's paper on the in-situ and in-field aging monitoring technique for embedded SRAM has been accepted for the publication in IEEE Transactions on VLSI Systems. Congrats, all the coauthors!
May, 2018: Jiangyi's paper on the 96-channel DSP-PMU SoC for a neural implant is accepted for the publication in IEEE European Solid-State Circuits Conference (ESSCIRC). This chip can perform the end-to-end signal processing for intercellular-spike based motor intention decoding at sub-microwatt power consumption, which is 10X lower than prior arts. The chip also features error-based power management hardware for the nanowatt DSP core. It can automatically find the setting of the integrated switched-capacitor DCDC converter to minimize the total power dissipation of the SoC. This is a collaborative work with Joonseong Kang, Seungchul Jung, and Sang Joon Kim (Samsung SAIT). LINK
May, 2018: Josh's journal paper on ultra-compact thermal sensor for dynamic thermal management is accepted for the publication in the special issue of Journal of Low Power Electronics and Applications. Congrats!
May, 2018: Dongkwun's paper on the compact switched-capacitor converter design based on the better-than-worst-case design methodology is accepted for the publication in 2018 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED). This is a collaborative work with several researchers from Intel Circuit Research Lab (CRL) (Drs. Minki Cho, Ram Krishnamurthy, Seongjong Kim, Suhwan Kim, Suyoung Bang) LINK
May, 2018: Sheng's paper on the ML processor for monitoring and blacklisting the security attack via power management subsystems is accepted for the publication in 2018 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED). This is a collaborative work with Dr. Adrian Tang and Prof. Simha Sethumadhavan. Congrats! LINK
Mar, 2018: Doyun's paper on self-triggering event-driven digital LDO circuits is accepted for the publication in 2018 Symposium on VLSI Circuits. Congrats! LINK
Mar, 2018: Zhewei's paper on in-memory computing macro for binary and ternary deep neural network is accepted for the publication in 2018 Symposium on VLSI Circuits. Congrats! This is a collaborative work with Prof. Jae-sun Seo's group in ASU. LINK
Mar, 2018: Prof. Seok is promoted to the associate professor.
Mar, 2018: Prof. Seok will serve as a technical program committee member (digital circuits) for IEEE International Solid-State Circuits Conference (ISSCC) from 2018.
Mar, 2018: Prof. Seok is elevated to the grade of IEEE Senior Member.
Jan, 2018: Our group will present an invited paper on in-situ and in-field transistor aging monitoring and compensation for logic and memory circuits in 2018 IRPS. LINK.
Dec, 2017: Jiangyi's paper on the transformable cache for a temperature sensor and a PUF is accepted for publication in the JSSC special issue. Congrats! LINK.
Oct, 2017: Minhao's paper on the 1-microwatt voice activity detector design is accepted for publication in 2018 ISSCC. Congrats! LINK.
Aug, 2017: Doyun's paper on the event-driven compact LDO design is accepted for publication in JSSC. Congrats! LINK.
July, 2017: We will present two collaborative papers in the upcoming MICRO. LINK.
Jun, 2017: Wei Jin's paper on near and sub-Vt pulsed latch pipeline is accepted for publication in JSSC. Congrats! LINK.
Jun, 2017: Two papers will be presented in 2017 European Solid-State Circuits Conference (ESSCIRC) this Sep. Congrats on Josh and Joao! LINK.
May, 2017: Our paper on the energy-harvesting converter adpative to power mismatch is accepted for IEEE Journal of Solid-State Circuits (JSSC). Congrats Jiangyi! LINK.
May, 2017: Joao receives the prestigious Qualcomm Innovation Fellowship (QinF). This is a joint award with Tom Repetti (PhD. student in Prof. Martha Kim's group). Congrats to the team! LINK.
May, 2017: Two papers, one on continuous-time comparator and the other on dynamic thermal management, are accepted for IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED). Congrats Sung, Doyun, and Pavan.
Feb, 2017: The paper titled “A Technique to Transform 6T-SRAM Arrays Into Robust Analog PUF with Minimal Overhead” is accepted for IEEE International Symposium on Circuits and Systems (ISCAS). Congrats Jiangyi and Teng.
Jan, 2017: The paper titled “An Area-Efficient Microprocessor-SoC with an Instruction-Cache Transformable to a Temperature Sensor and a Physically Unclonable Function” is accepted for IEEE Custom Integrated Circuits Conference (CICC). Congrats Teng, Jiangyi, and Minhao. This work is a collaborative work with Prof. Peter Kinget.

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