Guidelines for Schematic Editing for Analog & RF
- Only use 4-terminal MOS symbols.
This forces you to think where the body should be connected. For pMOS
transistors and nMOS transistors in a separate well the option exist to
connect the body to the source. Also if you want to do (manual)
substrate noise simulations you need access to the body terminal.
Power Supply and Ground
- Do not use the special VDD symbols anywhere.
- Do not use the special GND symbols inside your cell schematics.
- Each subcell needs to have a VDD and VSS I/O pin.
- Only use one GND symbol in your toplevel (testbench) schematic so
the simulator has a reference node.
Power supplies and grounds are circuit nodes like any other nodes. The
only thing that sets them apart is that a lot of components are
connected to them compared to the number of components connected to
signal nodes. Using special symbols inside subcells results in a lot of
implicit connections that cannot be undone and are hard to
trace. Moreover you cannot do any power supply or ground noise
simulations on individual blocks or subsections of your circuit. In the
layout the supplies and ground are actual nodes. To model the physical
reality you often need to include series resistance and inductance or
decoupling capacitance at different locations. This is not possible if
everything is globally connected through special symbols.
Naming and Connections by Naming
- Avoid global names.
- Do not make any connections by naming. Use wires to connect nodes
Global nodes have the same problems as outlined above for power supplies
and ground. Global nodes do not physically exist. Also connections in
schematics made by giving the nets the same name are very difficult to
trace. Changes to the schematic might overlook these
connections. Connections by naming can simplify the look of a schematic
compared to a jungle of wires, but that is deception. If the circuit
requires complicated routing, that should be obvious from the schematic.
Hierarchy and Symbols
- All interactions between the sub cells and the higher up cells
needs to be through I/O pins. Do not make connections through global
- Use symbols with the inputs at the (top) left side, the
outputs at the right side, bias and control at the (bottom) left side,
power supplies at the top and ground at the bottom.
- Try to maintain the same hierarchy in schematics as in the
layout. This simplifies layout-versus-schematic checks.
- Keep the positve supply rail at the top of the schematic.
- Keep the negative supply rail at the bottom of the schematic.
- Keep all input, control and bias pins lined up at the left side.
- Keep all output pins lined up at the right.
- Do not put any I/O pins in the inside of the schematic
- Keep the signals going from the left to the right in your
Full Chip Schematics and Simulation
- Have a top cell that has an indentical interface as your final
chip die. For every bondpad you have a I/O pin in the cell symbol.
- (If applicable) Make a schematic and cell that has the same
interface as your package and add a package model.
- Simulate your chip in a testbench that mimics your measurement
setup and uses the packaged chip symbol.
Feel free to contact me with any suggestions for changes. This page is
(and will probably remain) work in progress. Graphics would be a nice
addition. If you have any you are willing to share, please send
them. Thanks. -- PK