Welcome to the home page of EE6901 "Topics in Electrical and Computer Engineering -- Advances in Phase Locked Loops."

This graduate course will focus on the design and analysis of advanced phase locked loops. Check the syllabus for a more detailed description.

Why this course?

All modern electronic system-on-a-chip (SoC) devices that empower the computing and communication gadgets of our cyber society rely on phase locked loops (PLLs) to provide timing or frequency references. More importantly, the performance of PLLs often determines the overall system performance that can be achieved in wireless communications or high-speed serial communications. They are further essential for the generation of multiple, flexible clocks for SoCs and digital computing devices. With increasing demands for more data capacity and increased computing power, higher frequencies and higher bandwidths are required which continue to push the PLL requirements and make their performance even more critical for the overall system. PLLs further typically need to be integrated with large digital functions in nanoscale CMOS technologies resulting in challenging system and circuit design problems.


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