Design Rule Check Verification of Layout Using Cadence's
If you haven't read the CAD tool information page, READ THAT FIRST.
In this handout, we are going to learn the following :
Before running Assura, please create a file in your home
directory called assura_tech.lib. In this file, add the single line:
- Running Design Rule Check (DRC) verification on custom built layouts.
- Running Layout Vs Schematic Check (LVS) verification on custom built layouts.
DEFINE TSMC025 /usr/tech/tsmc025/assura/LVS_RCX
Although designers might
be conscious of the design rules when performing the layout, there is a
possibility of overlooking and thus violating the design rules. So,
the DRC is a step taken to prompt us of any violations. This step
is important because the violation of any design rules would result in
a higher probability, and in some cases an absolute certainty, that the
fabricated chip does not work as desired. Very simply, DRC can be thought
of as verifying whether the drawn layout is made in accordance with given
constraints (called DRC rules) or not.
To run DRC in our cadence setup, do the following :
- Save the layout and choose
Tools --> Assura . You will see
that a new pull down menu named "Assura" appears on your layout window.
- Now choose
Assura --> Run DRC.... Fill in the form as follows :
"Layout" field shows "dfII"
"Library" field shows your current library name
"Cell" field shows your current cell name
"View" field shows "Layout"
"Run directory" field shows any valid directory in your home (preferably the one where you want to store intermediate files).
"Rules File" field shows
All other fields are optional or default. So don't worry about the rest.
- Ready to run DRC. Hit "OK". If it prompts that "RSF file exists/DRC data exists...overwrite?",
- A progress form will appear showing Assura DRC is in progress. Wait for a few seconds until the DRC run is over.
- After the run is over, it will prompt you to view results. Hit "OK" and a new window will appear showing which violations and where. Clicking on specific errors on the errors window, will also lead you to the exact location of the error in your layout with error area highlighted.
- Correct the error and re-run DRC as described above.
- Repeat the process until the design contains NO DRC errors.
- At this point, your design is DRC error free.
After completing DRC , you are ready to run LVS check. LVS (layout versus Schematic)
is another important verification. While DRC just checks if your layout follows the
rules set by a technology, LVS on the other hand, verifies if your layout
matches the transistors defined in your schematic or NOT. Therefore, LVS program needs both your "schematic" as well as
"layout" files as its input and compares them. Before running LVS,
make sure that :
- You have both "schematic" and "layout" views under the same cell name in the same library. If
you don't , copy the schematic of your circuit (for which you have drawn your layout) under the same cell name. (This is not mandatory, but makes life simpler).
- You have placed pins on your layout which correspond one-to-one with schematics i.e. same name and same number of pins in both schematic and layout views.(for "how to place pins", look in the layout tutorial posted on the webpage)
Having done the above two things, you can run LVS as follows :
- Choose "Assura --> Run LVS...". Make sure the layout and schematic fields
show the correct location for "library" and "cell".
- Choose "run directory" as you did while running DRC.
- choose "Compare rules" as "/usr/tech/tsmc025/assura/LVS_RCX/compare.rul".
- All other options should be set by default.
- Hit OK and wait for results. It will either tell you that your layout
is "LVS clean" or otherwise it will open up an error window.
- Generally, LVS errors are hard to understand especially for first timers.
Since your circuits are very small, the most probable errors that you will have will be the result of following :
1. You forgot to put substrate and n-well contacts. (Most common type)
2. You forgot to put the same name and same number of pins in your layout as in your schematic.
3. If after satisfying above, you still have LVS errors, recheck your layout making sure
you have done correct wiring connections between various nodes.
- This completes the LVS check. At this point you can be quite sure of the fact that your
layout if fabricated will WORK but performance depends upon the quality of your layout
(Area and node capacitances).