CISL Tutorials

Design Rule Check Verification of Layout Using Cadence's Assura

If you haven't read the CAD tool information page, READ THAT FIRST.

In this handout, we are going to learn the following :

Before running Assura, please create a file in your home directory called assura_tech.lib.  In this file, add the single line:

DEFINE TSMC025 /usr/tech/tsmc025/assura/LVS_RCX

Although designers might be conscious of the design rules when performing the layout, there is a possibility of overlooking and thus violating the design rules.  So, the DRC is a step taken to prompt us of any violations.  This step is important because the violation of any design rules would result in a higher probability, and in some cases an absolute certainty, that the fabricated chip does not work as desired. Very simply, DRC can be thought of as verifying whether the drawn layout is made in accordance with given constraints (called DRC rules) or not.

To run DRC in our cadence setup, do the following :

After completing DRC , you are ready to run LVS check. LVS (layout versus Schematic) is another important verification. While DRC just checks if your layout follows the rules set by a technology, LVS on the other hand, verifies if your layout matches the transistors defined in your schematic or NOT. Therefore, LVS program needs both your "schematic" as well as "layout" files as its input and compares them. Before running LVS, make sure that :

Having done the above two things, you can run LVS as follows :