April 7, 2008
EE Conference Room, 13th Fl.
Speaker: Naveen Verma, Massachusetts Institute of Technology
Ultra-low-power electronics is forging brand new applications including sophisticated biomedical implants, ubiquitous sensor networks, and portable multimedia devices. To enable these, however, orders of magnitude reduction in energy consumption is required, implying a need to target device, circuit, and architecture level energy trade-offs.For instance, circuit trade-offs, like supply-voltage reduction, allow us to improve energy-efficiency in exchange for performance, which is often a secondary requirement in these applications. Unfortunately, however, device realities, such as variation, oppose our ability to apply these trade-offs in the aggressive manner required. I will show, using the critical example of SRAMs, how these can be overcome efficiently by the general techniques of circuit-assist, where some devices serve only to improve the low-energy characteristics of others, and redundancy, where many "cheap" elements provide a statistical pool from which one adequate element can be selected. These techniques will be taken further in the case of both an SRAM and an ultra-low-energy ADC to transfer the severe constraints of the energy-limiting sub-circuits to more energy-efficient ones, in order to reduce total energy. Once we understand how to maximize the efficiency of the circuit blocks, I will show how they can be made adaptable to respond to the system-level use-case, so that the trade-offs associated with the energy limiting component, which changes dynamically, can continuously be optimized. Finally, the system-level interaction of various heterogeneous circuit blocks, that each use their own mode of processing, will be exploited by applying hardware-energy-centric algorithm design that aims to reduce the burden on high-energy circuits in favor of low-energy ones. The example of a continuous seizure detection system, currently in development, will be used to show how this can yield over an order of magnitude further reduction in system energy.
Naveen Verma received the B.A.Sc. degree in Electrical and Computer Engineering from the University of British Columbia, Vancouver, Canada, in 2003. He received the M.S. degree from the Massachusetts Institute of Technology (MIT) in 2005. He is currently pursuing the Ph.D. degree at MIT where his research interests include low-power mixed-signal circuits and systems in the areas of analog-to-digital converters, SRAMs, and implantable biomedical systems. Mr. Verma is the recipient of the Intel Foundation Ph.D. fellowship and the NSERC Postgraduate fellowship.